NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/sys/mac/hardware/21851

Internet Message Format | 1992-11-18 | 3.2 KB

Path: sparky!uunet!news.tek.com!tekig7!tekig5!drchambe
From: [e-mail] (Dennis Chamberlin)
Newsgroups: comp.sys.mac.hardware
Subject: Re: About IIsi upgrade heat
Message-ID: <[e-mail]>
Date: 18 Nov 92 18:14:03 GMT
References: <[e-mail]>
Sender: [e-mail]
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 63

In article <[e-mail]> [e-mail] writes:

>    When you increase the clock speed to 25 MHz, which is a 25% increase
>in clock speed, you are NOT increasing the current through the chip by 25%,

>Since the formula for power is P=I^2*R, a current that was 1.25% of the
>original current would produce an increase of (1.25)^2=1.563%.

>This means that each clock cycle will produce heat for a SHORTER amount of
>time, and that therefore even though there are 5 million more clock cycles
>you end up with no more heat than before.
>
>I hope that some EE freakmo who can explain it better than
>me will write in and do so.

Most of the power dissipated in the chip occurs during the switching
transitions. The R of the I^2*R is very low during the on-time and the I
is zero during the off-time. However, the transitions are not instantaneous
and a plot of power over the switching cycle shows big spikes when both I
and R are significant (during the switch). There are more of these transitions
and thus more power spikes at the high clock rate.


>I have no idea what the
>increase in clock speed will do to the impedance of the chip.

...but it is possible that some
>inductance value of the chip would change with the increase in clock speed,
>and thus change the power dissipated by the chip.
...I would like to know. But, these ideas sound reasonable to
>me,...

Your ideas are indeed reasonable, but I think you assumed the transitions
take zero time and thus dissipate no power. Actually, they account for the
majority of the power.
Also, although the inductances and capacitances represent impedances to fast
signals, this type of impedance does not dissipate power. Think of springs
vs. shock absorbers or brakes.

...I have a hypothesis. Here goes: In some chips,
>manufacturing defects and abnormalities sometimes might result in some current
>path in the circuit being too close to another circuit path, resulting in
>more interference with each other. Now, an oscillating current will radiate
>radio waves according to physics, so these radio waves might be interfering
>with each other or there could be some capacitance thing or any number of
>types of interference between the two traces. Now, an increase in frequency
>generally means an increase in power broadcast for radio waves and such, and
>it could be that this increase in the radio wave energy pushes the chip over
>the edge, to where the interference between traces finally proves fatal for
>the chip and you get false signals as a result.

You're absolutely right. The extra noise generated will tend to reduce
operational tolerances at the higher speed. However, timing considerations
may be more important. As speed increases, Clock transitions will eventually
crowd the data transitions to the point the data "read" becomes unreliable.


                 sincerely,

            EE Freakmo