NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/sys/amiga/hardware/19646

Internet Message Format | 1992-11-15 | 2.7 KB

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From: [e-mail]
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 14.xx & 7.xx Mhz, why?
Message-ID: <[e-mail]>
Date: 15 Nov 92 23:15:42 GMT
References: <[e-mail]> <[e-mail]>
Organization: Computer Centre, Monash University, Australia
Lines: 38

[e-mail] (Dave Haynie) writes:
> [e-mail] (Stig Arne Olsen) writes:
>>
>>Can some guru :-) here tell me why C= are clocking the processors below what
>>they were made for? They do not seem to do it with the faster processors,
>>but why are the Mc68000 just 7 and Mc68020 in the A1200 14Mhz? Has it something
>>to do with dma-cycle timing?
>
> It has everything to do with Chip RAM timing.  Chip RAM lives on the synchronous
> Chip bus, which is based on a 7.09-7.16MHz clock (actually, two of them).  It's
> much simpler to interface a processor to this bus if you make its bus clock the
> same clock as used for the Chip bus.  There are a number of problems that you

        I think Stig was asking *why* those clock speeds were chosen in
the first place. As David said, the speed of CHIP ram is the key. The speed
is based on the PAL and NTSC video frequencies (PAL = 7.09 Mhz, NTSC =
7.14 (?) Mhz). The origional Amiga designers wanted a system that could
easily combine it's video signal with standard video broadcast signals
(PAL & NTSC), so they decided to set the master clock speed of the Amiga
to be the same as the video frequency used in that country (PAL Amigas
are slightly slower than NTSC Amigas). The reason why CHIP ram is the
key is because that's where the video data is displayed from, so it
was set to synchronize with the PAL or NTSC video broadcast frequency.

        When accelerating an Amiga you have 2 choices. Either use an
exact multiple of the master clock speed (eg 14.x Mhz) or have your
CPU run on it's own seperate clock (any speed you like). By running
the CPU on it's own clock, you can make better use of that chip's top
limit, but your accelerator has to be able to access CHIP ram at
7.x Mhz, so the accelerator design needs to be more complicated to
guarantee that CHIP ram access is performed at the correct speed.
By using an exact multiple of 7.x Mhz, you don't need the extra
hardware to make sure the timing is correct, but you don't get the
best possible speed from the CPU chip.

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