NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/sys/amiga/hardware/19644

Internet Message Format | 1992-11-15 | 3.0 KB

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Newsgroups: comp.sys.amiga.hardware
Subject: Re: Parity
Message-ID: <[e-mail]>
From: [e-mail]
Date: 16 Nov 92 11:10:01 +1000
References: <[e-mail]> <[e-mail]>
Organization: MITS
Nntp-Posting-Host: ratty
Nntp-Posting-User: lewis
Lines: 51

In article <[e-mail]>, [e-mail] (Chuck Goodhart) writes:
> In article <[e-mail]> [e-mail]
> (Ethan Dicks) writes:
>>EDC (Error Detection and Correction) is also known as ECC (why, I don't
>>know).  On Unibus VAXen, ECC memory is 10 bits/byte; it can *correct*
>>single bit errors and detect double bit errors.
>
> Could you either post the details about how VAXen achieve this,
> or point out the flaw in the following argument:
>
> With 10 bits you have 2^10 (=1024) different bit patterns.  In order to
> encode 8 data bits you need 2^8 (=256) of these to be valid.
>
> Each valid pattern generates a set of 11 patterns, one valid and 10
> which are a single bit flip away from the valid pattern.  None of
> these 10 can be valid patterns, or a single bit error could go
> undetected, let alone uncorrected.  Further, none of them can be
> a single bit flip away from some other valid pattern, or you would
> have single bit errors which would have two (or more) equally likely
> correction paths, thus being uncorrectable.
>
> At this point, however, we need 256*11 (=2816) different patterns,
> since there can be no overlap among the 256 sets of 11 patterns.
> --
> Chuck Goodhart, [e-mail]

Well, from the VAX Hardware Handbook, the VAX 11/730 handles it this way:

"The ECC scheme used in the memory subsystem is capable of detecting a single
or double bit error.  It is also capable of correcting all single bit errors.
This is accomplished by storing eight check bits, along with the 64 data bits
in each memory location (i.e. quadword access to memory).  Each check bit is
generated by parity-checking selected groups of data bits in the given data
quadword.  When parity is again checked during a read, an incorrect bit will be
detected by the parity-checking logic and will develop a unique 8-bit syndrome
which will identify the bit in error.  Error correction logic may thus correct
the bit in error.  There are 72 unique syndromes pointing to individual bits in
the coded quadword."

This may not explain how the any memory connected to a Unibus adapter may error
correct, but it does indicate how by using a single parity bit per byte, when
combined into a quadword, can be very useful.

Somewhere I have a document on the actual method used to achieve this.  I shall
have to look for it.

--
David Lewis,

Internet:    [e-mail]
Phone:        [phone]        Fax:        [phone]