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- Path: sparky!uunet!zaphod.mps.ohio-state.edu!rphroy!albert!tkacik
- From: tkacik@hobbes.cs.gmr.com (Tom Tkacik CS50)
- Newsgroups: comp.sys.3b1
- Subject: Re: Unix system V question
- Message-ID: <93473@rphroy.ph.gmr.com>
- Date: 16 Nov 92 15:17:49 GMT
- References: <1992Nov14.214445.24434@athena.mit.edu>
- Sender: news@rphroy.ph.gmr.com
- Reply-To: tkacik@hobbes.cs.gmr.com
- Organization: GM Research Labs
- Lines: 19
- Nntp-Posting-Host: albert.cs.gmr.com
-
- In article 24434@athena.mit.edu, hhc@athena.mit.edu (Hong-Hsiang Chen) writes:
- > BTW, who knows what MMU chip the 3b1 is using? I've poked around the
- > hardware but can't seem to identify the MMU...
-
- The 3b1 uses a home brew memory management scheme. There is no MMU. It is done
- using some memory chips and TTL logic. It implements simple 1 level memory
- mapping, with the memory chips as the page table.
-
- There are 1024 4K pages, thus giving the 4MB virtual memory limit.
- Along with the 12 address bits for each page, there are 4 other protection bits.
- I believe these are read, write, and execute permission, plus a page modified bit.
-
-
- --
- Tom Tkacik
- GM Research Labs
- tkacik@hobbes.cs.gmr.com
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