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- From: ekearns@bbn.com (Edward Joseph Kearns)
- Newsgroups: comp.lsi.testing
- Subject: Re: board test
- Date: 19 Nov 1992 01:21:17 GMT
- Lines: 35
- Message-ID: <lglr0dINN5oj@news.bbn.com>
- References: <1992Nov18.170306.4244@titan.ksc.nasa.gov>
- NNTP-Posting-Host: bbn.com
-
- dlr@testeng.ksc.nasa.gov (Doug Reed) writes:
- ....
- >Anyway, let me know if I'm off-base here or what.
-
- >Regards, Doug
-
- You are more than welcome to comp.lsi.testing. In fact 1149.1 is
- exactly why I came here a few weeks ago. There was considerable
- response to my request for experince on the topic of boundary-scan,
- and by judging the responses I received, you will find no better
- forum to ask such questions. Apparently this is where the 1149.1
- experts occasionally hang out.
-
- For those that may be wondering, I'm still digesting all the
- information I was sent. I've gone ahead and set up in-house demo's
- with TI and Fluke/Philips. I've spoken with Alpine Image Systems,
- National Semiconductor, Teradyne, Tektronix...
-
- I ordered and received some books from IEEE. "The Test Access Port
- and Boundary Scan Architecture" by Maunder and Tulloss, and also
- "Integrating Design and Test: Using CAE Tools for ATE Programming"
- by Ken Parker, so I've been busy reading.
-
- So Doug, While I'm trying to formulate my next question, let's hear
- one from you! Have you had any 1149.1 implementations tossed your way
- in board test. Did your testers handle the task. Who wrote the b-scan
- test vectors? Did you have any internal scan paths? Multiple paths?
- What where the major hurdles? Did anything go completely wrong?
-
- Anyone else...?
-
- Ed Kearns
- BBN Systems & Technologies
- Bellevue, Washington
- 206-957-3271
-