NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/lang/verilog/436

Internet Message Format | 1992-11-19 | 1.8 KB

Path: sparky!uunet!think.com!unixland!wellspring!elliot
From: [e-mail] (Elliot H. Mednick)
Newsgroups: comp.lang.verilog
Subject: Memory Addressing in verilog
Distribution: world
Message-ID: <[e-mail]>
References: <[e-mail]>
Date: Thu, 19 Nov 92 15:44:23 GMT
Organization: Wellspring Solutions, Sutton, MA.
Reply-To: [e-mail]
Lines: 31

In article <[e-mail]> [e-mail] writes:
 > My question is: does verilog do any bounds checking on index values to register
 >                 arrays or do I have to implement such checks myself?

You have to implement the checks yourself.  Note that in RTL coding, you
don't want to do checking unless the hardware you are designing is going to
do range-checking.  In behavioral-level coding, you can do whatever you want.

One technique that you ca use is to have a seperate "integrity-check"
module that continually tests things like index ranges and detects
other illegal conditions.  This module would be a 2nd top-level module
(that is, niether of the top-level module instantiate each other) and
reference variables within the simulation model by hierarchical names
so it would be non-intrusive.  This way, you can have an RTL model,
perhaps for synthesis, but with the range checking not part of the
actual RTL model.  For example:


module integrity;

// monitor 'index'
always @(my_module.index)
  if (my_module.index < 0 || my_module.index > `MAX_INDEX)
     $display ("Index out-of-bounds detected at time %t!", $time);
...
endmodule

--
Elliot H. Mednick                                        P.O. Box 150
Wellspring Solutions                                     Sutton, MA. 01590
[e-mail]                                    [phone]