NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/arch/10849

Text File | 1992-11-17 | 3.2 KB | 72 lines

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From: [e-mail] (Blair Phillips - Digital)
Subject: Re: DEC Alpha AXP System INTEGER Performance
Message-ID: <[e-mail]>
Keywords: Alpha, AXP, SPEC, DEC, INTEGER
Lines: 58
Sender: [e-mail] (USENET News System)
Reply-To: [e-mail]
Organization: Digital Equipment Corporation
References: <[e-mail]> <martin.721554717@bert> <[e-mail]> <[e-mail]>
Date: Mon, 16 Nov 1992 23:19:49 GMT


In article <[e-mail]>, [e-mail] (Greg Pavlov) writes:
>
>In article <[e-mail]>, [e-mail] (John DiMarco) writes:
>> In <[e-mail]> [e-mail] (Greg Pavlov) writes:
>>
>> >  The SPECint92 values seem somewhat low, in terms of processor MHz.  Any
>> >  known reasons why ?  Essentially, our R3000-based systems, at 40 MHz,
>> >  have a SPECint92 (measured by DEC) that is apx. 40% of an ALPHA-based
>> >  system at 133 MHz.
>>
>> There are two ways of making processors fast. One is making them do more
>> per clock cycle. The other is making them run at a higher clock rate.
>>
>  Of course.  But you are summarizing my question, not answering it.
>
I'm tempted to say:
"Go read Hennessy & Patterson, then you will see that John DiMarco *does*
answer your question"

However...

The major design decisions in the Alpha AXP architecture were biased towards
high clock rates rather than high SPECmarks/MHz. The decisions were simulated
using real code traces to validate the choices.

A good example is the lack of 8 and 16 bit load and store instructions.
Providing these would have added a complex multiplexor in the critical path
from the internal cache to the register file. It would have forced either a
longer cycle time, or an extra cycle for *all* load/store instructions.
Most real programs will use the runtime libraries for string manipulation, and
anyone serious about speed won't access single bytes very often, even on a VAX,
so trading off the byte access against cycle time is beneficial in almost all
cases except artificial benchmarks (e.g. Dhrystone).

At the other extreme, it would be possible to implement most of the VAX or
M68xxx instructions in a single cycle, but your cycle time would be measured in
microseconds rather than nanoseconds! You would get a really terrific
SPECmark/MHz ratio, even if the absolute SPECmark was << 1.0

Patterson & Hennessy have lots of examples of these sort of tradeoffs, if you
are interested.

The question is not
"Why does chip XYZZY have a higher SPECmark/Mhz than an Alpha AXP chip?"
but
"Why can't chip XYZZY run at a high enough clock rate to give the same SPECmark
as an Alpha AXP chip?"

So far, the HP PA-RISC architecture is the only microprocessor architecture
that is close.
--
----------
Blair Phillips                    [e-mail]
Digital Equipment Corp (Aust) P/L        Phone: [phone]
Canberra, Australia                FAX  : [phone]
{Any opinions expressed are my own, not those of Digital Equipment Corporation}