NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/sci/electron/13435

Internet Message Format | 1992-07-27 | 3.6 KB

Path: sparky!uunet!comp.vuw.ac.nz!windy!grace!srgxnbs
Newsgroups: sci.electronics
Subject: Re: 20 Bit Counter?
Message-ID: <[e-mail]>
From: [e-mail]
Date: 28 Jul 92 13:37:49 +1200
References: <[e-mail]><[e-mail]> <[e-mail]>
Organization: DSIR, Gracefield, New Zealand
Lines: 66

In article <[e-mail]>, <[e-mail]> writes:
> In article <[e-mail]>, [e-mail] (Eric
> Smith) says:
>
> Original post was about needing a 20-bit address generator for RAM.
>
>>You could use a CMOS counter 14-bit counter like the 4040.  Remember that
>>it needs CMOS input levels on the clock and reset lines.  Two of these would
>>get you 28 bits.  These are really slow, and since you would need two of
>>them anyhow, I think you're probably better of with 74xx parts.
>
> There is the HC remix of the 4020, 4040 chip.  They are now 74HC4020 and
> 74HC4040.  These are faster chip and blessed with 74HC drive capabilities
> and speed.  Do use them carefully.  Due to the rippling nature (each bit
> has an accumulated delay from the last one in the chain) and CMOS
> switching current, pretty bad ring on the output is possible.  I have
> witnessed  2V ringing on a badly done wire wrap board with these chips.
> I 'fixed' the problem by terminating the outputs to ground via 220 ohms
> resistors.  The ringing is reduced to below TTL thresholds.
>
> I pretty much use synchronous counters on all my designs - a side effect
> of doing VLSI course and working with PLD's.
>
> I would highly recommend using a series of synchronous counter described
> below or at the very least use latches on the outputs clocked by a
> different phase of the clock (ie hold the previous address until the
> new one settles down).  This reduces the chip count and optionally allows
> one to tristates the address generator for access from CPU side.
>
>>
>>If you need the counter to be fast enough to be able to read or write
>>the memory "instantly" after incrementing, you need to use synchronous
>>counters, like the 74xx163.  For a fully synchronous 20 bit counter, you
>>would need to have four gates to generate the *ET (or was it *EP) inputs
>>to each '163 after the first.  In practice you can tie the ripple carry
>>output of each counter to the *ET and *EP inputs of the next counter up.
>
>>There are probably some 8 bit synchronous counters also, in the 74xx500-699
>>range, but I don't know them offhand.
>
> 74LS469 is a 8-bit up/down counter.  I don't know whether it is
> synchronous or not.  It is missing from my really old TTL databook.
>
> Alternative is to implement the counter in a PAL/GAL chip if you know
> what you are doing and have the equipment to program it.  PLD's
> are kind of slow, but they allow a much more complex designs.
>
>>Eric
>
> K. C. Lee
> Elec. Eng. Grad. Student

This may have been suggested (or rejected) ...
If repetition rate is not important and any sort of random access is required
then an alternative would be to use cascaded bit shift registers instead.
minus = 20 times round small program loop to load each address.
plus = all 20 bits change synchronously
       speed advantage for address changes greater than approx 20
       relative to current address, ie constant access time independant
       of address
--
Bruce Spedding - Materials Science and Performance Group
SRGXNBS@???????????????????
Industrial Research Limited                Ph +64 [phone]
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