Organization: Macquarie University, School of Mathematics, Physics, Computing and Electronics
References: <jeremym.711852401@sfu.ca>
Date: Fri, 24 Jul 1992 00:02:05 GMT
Lines: 50
In article <jeremym.711852401@sfu.ca>, jeremym@fraser.sfu.ca (Jeremy Thomas McDonald) writes:
|> I was wondering if there are any PALs/GALs that have a large number of D flipflops. I need to implement two 12-bit counters and a 15-state FSM and and 8-bit
|> register. I also need three 8-bit I/O ports. I want to design a controller
|> to act as a pseudo-Dual port RAM controller, with a high speed 20ns RAM chip
|> (single ported) attached to one of the ports on the PAL/GAL, and the PAL/GAL
|> acting as a time slicer for the RAM. One port on the PAL is read-only, the
|> other is write-only.
|> Any help in this area would be much appreciated, as going with external
|> MSI logic eats up tons of board space. Thanks.
|> e-mail to: jeremym@fraser.sfu.ca
|>
First, have you considered dual-port ram chips? IDT and Cypress both make parts
with reasonable speed. Assuming that you've discarded this option:
Sounds like you need to head toward an FPGA. Look at parts from Xilinx (3000
series - the new 4000's are _very_ pricey). These parts download their
configuration from a little 8 pin serial prom on power up. Alternatively, if
you have a uP, you can load them with a word-wide dump. These things will run
with a 50MHz clock too!
Actel and Lattice also make FPGA's - the Lattice parts are known as pLSI.
However, you don't really need to go this far. A dual port Ram controller can
be made much more simply if a simple time-slice (50% access each) is required and
you can live with some latency of response. If you really need ultra-speed, then
you will indeed need to look at the more complex solution. Otherwise:
Treat the whole dual port unit as a synchronous solution that alternates between
a write cycle and a read one. Consider using a RAM such as IDT71982 (16kx4 -
other depths are available - you don't mention how big you need the bank) that
has separate inputs and outputs. Then you won't need data bus buffering. You will
still need address bus tristate buffers though. A single PLD should be able to
handle the state machine - it has four major states: write cycle but no write
request; write cycle with a write request; read cycle but no read request; read
cycle with a pending read request.
Depending on the address bus width, you should be able to get away with five
