NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/unix/bsd/3258

Internet Message Format | 1992-07-30 | 2.7 KB

Xref: sparky comp.unix.bsd:3258 comp.os.linux:7095 comp.periphs.scsi:3828
Newsgroups: comp.unix.bsd,comp.os.linux,comp.periphs.scsi
Path: sparky!uunet!mcsun!sun4nl!relay.philips.nl!philica!adrie
From: [e-mail] (Adrie Koolen)
Subject: Re: Query: Drivers for AHA >1522< ?
Message-ID: <[e-mail]>
Organization: Philips Consumer Electronics, Eindhoven, The Netherlands
References: <[e-mail]> <[e-mail]> <[e-mail]>
Date: Fri, 31 Jul 1992 06:42:43 GMT
Lines: 40

In article <[e-mail]> [e-mail] (Roy Neese) writes:
>In article <[e-mail]> [e-mail] (Drew Eckhardt) writes:
>> If you're talking about sustained transfer rate, it's going to be
>> faster to do polled I/O because you don't have the couple of clock
>> cycles associated with each bus on period - you just crank data
>> across the AT bus topspeed, 16 bits at a time.
>
>Nope.  Polled I/O can never be faster than bus master DMA as it takes
>twicw as many cycles to move each word doing polled I/O as it does for a
>bus master to move the same word.
>The overhead you speak of is for acquiring the bus, wchi takes 2 cycles
>and then of course it takes another 2 cylces to release the bus.  But to
>show a more subjective view.  Let's make some assumptions, good
>assumptions.  Let's say 1 cycle per word for bus master DMA and 2 cycles
>per word for polled I/O (you have to do a read and write for polled I/O,
>whereas bus masters do either a read or a write).  Now let's move 512
>bytes of data.  Let's see,... for polled that would be 1024 cycles and
>for a bus master 512 + 2 + 2 = 516.  Nuff' said.

Unless I misunderstand the conditions of your example transfer, I have to
disagree.

I assume that you mean "AT-bus cycle" when you talk about cycles. Clearly,
you can't transfer one word over the AT-bus in only one cycle. I was under
the impression that it takes some 6 or 8 cycles.

That would seem to be a bigger advantage for bus mastering controllers, but
you're wrong in the assumption that the write into (or read from) memory
is done over the AT-bus. Normally, this is done over the local CPU bus
(33 MHz?), which is much faster than the AT-bus (8 MHz?).

Furthermore, it would be unwise to take the AT-bus for 512 cycles. Under
normal 1542b operation, the bus freed after some 7 cycles, so the overhead
of getting and releasing the bus is bigger.

I agree that bus mastering I/O is faster than polled I/O over the AT-bus,
but not with the factor you indicate.

Adrie Koolen ([e-mail])
Philips Consumer Electronics, Eindhoven, the Netherlands