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- Newsgroups: comp.sys.sgi
- Path: sparky!uunet!mcsun!sun4nl!dutrun!donau!dutecai!reinoud
- From: reinoud@dutecai.et.tudelft.nl (R. Lamberts)
- Subject: Re: Memory upgrades for R4000 Indigos
- Message-ID: <1992Jul25.163158.19280@donau.et.tudelft.nl>
- Originator: reinoud@dutecai.et.tudelft.nl
- Sender: news@donau.et.tudelft.nl (UseNet News System)
- Nntp-Posting-Host: dutecai.et.tudelft.nl
- Reply-To: reinoud@dutecai.et.tudelft.nl (R. Lamberts)
- Organization: Delft University of Technology, Dept. of Electrical Engineering
- Date: Sat, 25 Jul 1992 16:31:58 GMT
- Lines: 33
-
-
- jsw@microunity.com (Jeff Weinstein) writes:
- > Actually neither is true. The main problem with the r3k indigo was that
- > there just wasn't room on the CPU board to put the chips that did the
- > memory interleaving/control, so they had to go on the back of the simms.
-
- That's a good reason indeed. The density of the Indigo pcb is quite
- impressive. I had considered electrical reasons for this design only,
- and found that timing could improve only marginally by placing
- interleaving stuff on the SIMM.
-
-
- steve@europa.esd.sgi.com (Loopy - the spineless boy) writes:
- > If you put the R3K and cache on one board, then you would have to drag the
- > high speed CPU bus down the connector to the read/write buffer (5 glue chips
- > and a gate array). This bus was marginal to begin with.
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
- If I'm interpreting the Kane architecture book correctly, then this bus
- does 2 transfers each clock. So that's 66 MHz - using quite ordinary
- CMOS I/O pads. Right, you don't want to force that one through such
- a connector!
-
- > It was definitely *NOT* our intent to ream the customer with custom SIMMS. Even
- > SGI's lowest cost machine designs refuse to make big sacrifices on performance
- > in order to cut the cost a little. No one here likes to design mediocre machines
- > !
-
- Fine with me :-).
-
- - Reinoud
-
-
-