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- Xref: sparky comp.sys.ibm.pc.hardware:20598 comp.os.os2.misc:25880
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- From: rrosen@cesl.rutgers.edu (Robert Rosenbaum)
- Newsgroups: comp.sys.ibm.pc.hardware,comp.os.os2.misc
- Subject: Re: Can I mix 70ns SIMMS with 80ns SIMMS
- Message-ID: <Jul.29.11.30.18.1992.24020@cesl.rutgers.edu>
- Date: 29 Jul 92 15:30:18 GMT
- References: <19088@fritz.filenet.com> <1992Jul28.172146.21250@njitgw.njit.edu> <l7cno9INN6v7@tokio.cs.utexas.edu> <veit.712407248@du9ds3>
- Followup-To: comp.sys.ibm.pc.hardware
- Organization: Rutgers Univ., New Brunswick, N.J.
- Lines: 24
-
- In <veit.712407248@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes:
-
- >The problem is not really the different access time, as long as the slowest
- >chipset is at least as fast as it should be for the processor clock
- >frequency (e.g. 70ns for 386/33 with 1 wait state, 60 for 0 WS).
-
- I'm confused about wait states. My calculator tells me that 33MHz is 30ns , not
- 60 ns. Now I hear that memory is often interleaved so that a given bank is
- usually not accessed on succesive clock cycles, but this is this guaranteed?
-
- In particular, is main memory usually interleaved or paged in cached systems?
-
- My memory was set to 5ws by thew people who built it. When I inquired about
- this, I was told that it's not critical, because the cache acts at 0ws. My cache
- is 64k, so the hit rate should be well over 90% (shouldn't it?), but it still
- seems like a high price for a cache miss. Can I lower this?
-
- My main memory is 8MB of 80ns DRAM (9 chip simms). My cache is 64k of 20ns SRAM.
- I have an i386DX-33Mhz system. (C&T motherboard)
-
- Comments, answers would be appreciated.
-
- Rob
- rrosen@caip.rutgers.edu
-