NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/sys/ibm/pc/hardware/20350

Text File | 1992-07-26 | 1.8 KB | 42 lines

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From: [e-mail] (Dave Hazen)
Subject: Help wanted with DMA programming.
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Organization: Math, Stats & CS, Dalhousie University, Halifax, NS, Canada
Date: Mon, 27 Jul 1992 01:48:53 GMT
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I am writing an interface program for a high speed digitizer to run on
a Mesa 6c23 system.  The target system is a 16 MHz single board system
which drives an 8 bit passive backplane.  The board has a chips & tech
82c230 system controller chip which emulates the 8237, etc from the
original PC.  The digitizer wants to transfer to memory using DMA channel
1 and needless to say I am having some trouble setting it up due to a
dearth of information on the details of setting up the transfers.

One thing that I have sorted out from an IBM PC-XT technical manual is that
the register for the high nibble of the DMA address (IO 0x80-0x83) is
accessed in a strange way (at least from my interpretation of the schematics)
channel 0 and 1 will have the high nibble loaded from 0x83
channel 2 will have the high nibble loaded from 0x82
channel 3 will have the high nibble loaded from 0x81

Have I got it right?
If so, how do I avoid a contention problem with chan 0 refresh cycles?

Any code fragments on programming DMA channel 1 will be greatly appreciated
by return mail

Thanks

dave
--
Dave Hazen                        BitNet: [e-mail]
Dept. of Oceanography             Telemail: dalhousie.ocean
Dalhousie University              Voice: [phone]
Halifax, NS CANADA B3H 4J1        FAX:  [phone]