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- Path: sparky!uunet!munnari.oz.au!mel.dit.csiro.au!yarra!pta!sphinx!usage!csdvax.csd.unsw.edu.au!89u7491
- From: 89u7491@csdvax.csd.unsw.edu.au
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: CPU cycles
- Message-ID: <1992Jul24.140511.2717@csdvax.csd.unsw.edu.au>
- Date: 24 Jul 92 04:05:11 GMT
- References: <jbickers.0bpc@templar.actrix.gen.nz>
- Organization: University of New South Wales
- Lines: 15
-
- In article <jbickers.0bpc@templar.actrix.gen.nz>, jbickers@templar.actrix.gen.nz (John Bickers) writes:
- >
- > My routine takes around 2920 cycles, but it's only happening about
- > 850 times a second. Multiplying the two tells me there's roughly
- > 2,500,000 cycles a second, when I expected ten times that (25MHz).
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- You have forgotten memory access times. Time taken to get/put data from memory
- is considerably longer than a CPU cycle, this will raise the expected numer of
- Cycles per instruction. Secondly the 68030 instruction cycle may not be running
- at 25Mhz, it may be some derivative of this? (I'm not sure here). Anyway isn't
- the 68030 pipelined, in which case all instructions should take 1 pipeline
- cycle once the pipe is full.
-
- Cheers
- -Trevor
-