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- Newsgroups: comp.lsi.testing
- Path: sparky!uunet!zaphod.mps.ohio-state.edu!moe.ksu.ksu.edu!ux1.cso.uiuc.edu!m.cs.uiuc.edu!haney
- From: haney@m.cs.uiuc.edu (Michael Haney)
- Subject: 1149.1 for Xilinx FPGA's
- Message-ID: <1992Jul24.193925.26219@m.cs.uiuc.edu>
- Summary: Has anyone put 1149.1 into a Xilinx 3k FPGA?
- Keywords: 1149.1 Xilinx
- Organization: University of Illinois, Dept. of Comp. Sci., Urbana, IL
- Date: Fri, 24 Jul 1992 19:39:25 GMT
- Lines: 16
-
-
- Does anyone have an 1149.1 implementation for the Xilinx 3k
- family that they would be willing to share?
-
- Specifically, I am thinking about putting boundary scan into
- an XC3042-based project that I am working on, and I am curious
- as to how many CLB's it will cost for the controller and the
- boundary cells.
-
- I don't want to use Xilinx's configuration readout; I wish to be
- JTAG compliant with other devices in the project...
-
- Any information would be welcome.
-
- Mike Haney
- haney@cs.uiuc.edu
-