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Internet Message Format  |  1992-07-23  |  836 b 
  1. Path: sparky!uunet!darwin.sura.net!mips!pacbell.com!iggy.GW.Vitalink.COM!widener!dsinc!pitt.edu!unix.cis.pitt.edu!europa!ynhst1
  2. From: ynhst1@europa.ee.pitt.edu (Y. Hsieh)
  3. Newsgroups: comp.lsi
  4. Subject: critical delay estimators
  5. Keywords: delay estimation
  6. Message-ID: <207802@unix.cis.pitt.edu>
  7. Date: 23 Jul 92 16:29:53 GMT
  8. Sender: news@unix.cis.pitt.edu
  9. Reply-To: ynhst1@europa.ee.pitt.edu (Y. Hsieh)
  10. Organization: Electrical Engineering, Univ. of Pittsburgh
  11. Lines: 10
  12.  
  13. Hi,
  14.  
  15.      Does anyone know of any tool that could estimate critical delay based on
  16. extracted cmos layout.  An old tool called crystal is the only tool that I know
  17. that estimates critical delay based on extracted layout.  Unfortunately, it 
  18. only handles nMOS, not CMOS.  Any help would be greatly appreciated.  Thank you
  19. in advance.
  20.  
  21. Yee-Wing Hsieh
  22. ynhst1@ee.pitt.edu
  23.