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- Newsgroups: comp.lang.vhdl
- Path: sparky!uunet!wupost!eclnews!cec2!jab3
- From: jab3@cec2.wustl.edu (John Alonzo Breen)
- Subject: Re: Resolved signals
- Message-ID: <1992Jul27.125746.9638@wuecl.wustl.edu>
- Sender: usenet@wuecl.wustl.edu (Usenet Administrator)
- Nntp-Posting-Host: cec2
- Organization: Washington University, St. Louis Mo.
- References: <memo.540055@cix.compulink.co.uk>
- Date: Mon, 27 Jul 1992 12:57:46 GMT
- Lines: 31
-
- In article <memo.540055@cix.compulink.co.uk> jmessenger@cix.compulink.co.uk writes:
- >
- >Here are a couple of apparently simple questions, but I can't find the
- >answers in the LRM or the interpretations:
- >
- >subtype RTYPE is RESOLVED INTEGER;
- >type ARR is ARRAY (0 to 1) of RTYPE;
- >
- >signal S: ARR;
- >
- >I know that RTYPE is a resolved subtype. But
- >is S a resolved signal? (I believe not)
- >Is S(0) a resolved sigal? (Who knows?)
- >
-
- This is basically what the Std_Logic and Std_Logic_Vector types in the
- 1164 package are, I believe. S would be a composite of resolved
- signals. This is important, because if S was itself resolved, you
- couldn't drive one element of S without having drivers for all the
- other elements in the same process.
-
- Unfortunately, this has the disadvantage that S is not implicitly
- convertible to an array of integers (although the elements of S are
- implicitly convertible to integers). In other words, if you had a
- port of type "ARRAY (0 to 1) of INTEGER", you couldn't directly
- connect it to a signal of type ARR without a conversion function.
- --
- John A. Breen |
- jab3@cec1.wustl.edu | This space unintentionally left blank
- johnb@hobbes.mdc.com |
- Tel: (314)234-4341 |
-