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- Newsgroups: comp.lang.vhdl
- Path: sparky!uunet!usc!zaphod.mps.ohio-state.edu!wupost!eclnews!cec2!jab3
- From: jab3@cec2.wustl.edu (John Alonzo Breen)
- Subject: Pin numbers in VHDL descriptions
- Message-ID: <1992Jul21.211346.2245@wuecl.wustl.edu>
- Sender: usenet@wuecl.wustl.edu (Usenet Administrator)
- Nntp-Posting-Host: cec2
- Organization: Washington University, St. Louis Mo.
- Date: Tue, 21 Jul 1992 21:13:46 GMT
- Lines: 14
-
- Has anyone come up with a "standard" way of adding pin number info to
- a VHDL component? I assume that it could be done with attributes
- (although in the 3+ years I've been using VHDL, I've never done
- anything with user-defined attributes :-), but I can see where there
- might be some problems, particularly if a port is an array.
-
- If anyone has any suggestions, I would appreciate hearing from you.
-
- Thanks.
- --
- John A. Breen |
- jab3@cec1.wustl.edu | This space unintentionally left blank
- johnb@hobbes.mdc.com |
- Tel: (314)234-4341 |
-