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- Path: sparky!uunet!mcsun!uknet!brunel!eepgcda
- From: Chijioke.Anyanwu@brunel.ac.uk (Chijioke D Anyanwu)
- Newsgroups: comp.lang.verilog
- Subject: Getting round verilog hierarchical structure
- Message-ID: <Bs23x4.330@brunel.ac.uk>
- Date: 27 Jul 92 16:46:15 GMT
- Organization: Brunel University, West London, UK
- Lines: 42
-
- Modules in Verilog are organised in a hierarchical structure which,
- presumably, is in keeping in line with standard programming practice.
- However, I've come up against situations when this rigid structure has
- been a problem.
-
- As a simple example, consider the system below in which A, B and C are
- modules (representing hardware blocks) with dedicated links to each other.
-
- _______
- | |
- | A |
- | |
- -------
- / |
- / |
- / |
- ------- |
- | | |
- | B | |
- | | |
- ------- |
- \ |
- \ |
- \ |
- -------
- | |
- | C |
- | |
- -------
-
- In developing a verilog model, A could instantiate B and C but, as far as
- I can see, this would then mean the link from B to C would not be possible
- as there is no way of directly linking a module to another module which it
- is neither instantiated by nor instantiates.
-
- I've usually been able to get round this using one of two methods of
- indirect linking (which I call transit and transmission) but while they
- work alright, it's just not the same as direct links and can be quite
- inconvenient. I'd like to know if anyone else has had this problem and if
- there is some hidden means of implementing direct links in such situations.
-
- Chijioke.
-