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- Path: sparky!uunet!zaphod.mps.ohio-state.edu!moe.ksu.ksu.edu!matt.ksu.ksu.edu!news
- From: holland@matt.ksu.ksu.edu (Rich Holland)
- Newsgroups: comp.lang.pascal
- Subject: Re: how long is a clock cycle (was source for DELAY procedure)?
- Date: 30 Jul 1992 17:07:39 -0500
- Organization: Kansas State University
- Lines: 73
- Message-ID: <159p7bINNrq6@matt.ksu.ksu.edu>
- References: <Bs7Hv8.Bqz@news.cso.uiuc.edu>
- NNTP-Posting-Host: matt.ksu.ksu.edu
-
- amead@s.psych.uiuc.edu (Alan Mead) writes:
-
- >But I see several problems. FlushKBD will, depending on how I
- >implement it, take a different amount of time to execute depending on
- >how many keystrokes are in the buffer.
-
- No it won't. Just make the Head and Tail pointers the same. It will
- do the same operation everytime you call FlushKBD, and it will clear
- any keystrokes (not overwrite them, just pretend they don't exist).
- Send mail if you need code to do this...
-
- >Also, the delay will be longer than period milliseconds by number*<the
- >time it takes to execute FlushKBD>.
-
- Yup, it will...you could profile FlushKBD though and find out how
- long it takes, using the above method. Since it will take the same
- amount of time (# of cycles) to execute every time, this factor can
- be figured in...
-
- >Which all seems to bear on the value of shorter. I think that the
- >bigger I make it, the less trouble I accrue from the other points.
-
- How's that?
-
- >And all this stuff would seem to be processor (even machine!)
- >specific. Different machines will execute FlushKBD at different
- >speeds.
-
- Yup, they will -- a 50mhz 486 will set two pointers equal MUCH faster
- than a 4.77mhz XT, won't it? :-)
-
- >Anyone have any suggestions? Anyone know where in the executable code
- >I can find the Delay procedure's initialization data?
-
- Sure. Here's what I did...maybe it'll help, maybe it won't:
-
- Just compile this and trace through it:
- Program Test;
- Uses CRT;
- Begin Inline($90/$90/$90/$90); Delay(500); Inline($90/$90/$90/$90) End.
-
- I traced it with TD 1.5 and it looked "normal" to me -- using the clock
- tick counter in the BIOS data area (i'm pretty sure). Here, look at the
- disassembly (from DEBUG):
-
- 4AFD:029E 8BDC MOV BX,SP
- 4AFD:02A0 36 SS:
- 4AFD:02A1 8B5704 MOV DX,[BX+04] ; grab the delay count
- 4AFD:02A4 0BD2 OR DX,DX
- 4AFD:02A6 7413 JZ 02BB ; if it's zero, fall out
- 4AFD:02A8 33FF XOR DI,DI
- 4AFD:02AA 8EC7 MOV ES,DI ; ES=0
- 4AFD:02AC 26 ES:
- 4AFD:02AD 8A05 MOV AL,[DI] ; AL=0:[0] ???
- 4AFD:02AF 8B1E4A00 MOV BX,[004A]
- 4AFD:02B3 8BCB MOV CX,BX ; CX=0:[4a] Clock tick count?
- 4AFD:02B5 E80600 CALL 02BE ; call the "short loop"
- 4AFD:02B8 4A DEC DX ; one less time...
- 4AFD:02B9 75F8 JNZ 02B3 ; if not (dx=0) call short loop
- 4AFD:02BB CA0200 RETF 0002
- 4AFD:02BE 26 ES: ; SHORT LOOP
- 4AFD:02BF 3A05 CMP AL,[DI] ; wait a bit...
- 4AFD:02C1 7502 JNZ 02C5
- 4AFD:02C3 E2F9 LOOP 02BE
- 4AFD:02C5 C3 RET
-
- See how it works? Does it help any?
-
- --
- Rich Holland | INTERNET: holland@matt.ksu.ksu.edu
- 419 Marlatt Hall | BITNET : holland@ksuvm
- Manhattan, KS 66506 | UUCP : ...rutgers!matt.ksu.ksu.edu!holland
- "Jesus saves...but Gretzky gets the rebound! He shoots! He scores!!"
-