In article <l7duqeINN8gr@male.EBay.Sun.COM> miket@beav.EBay.Sun.COM writes:
>I'm looking at three chips.
>
> 56156 @ 33ns/instruction
> 320c50 @ 35ns/instruction
> dsp1610 @ 25ns/instruction
>
>Has anyone done a comparative analysis of these three chips? It's pretty tough
>to determine which of these would be best. For instance, just yesterday I
>noticed that an external write on a c50 takes two cycles and if a read precedes the
>write, the write takes 3 cycles. This is a pretty serious hit if you need to do
>a lot of memory accesses. This jucy peice of information is not listed in the data
>book at all until you get to the wayyyyyyy back where the timing diagrams are and you
>look at the smalllllllll print. This penalty doesn't exist in the C25 becuase this part uses a two-phase clocking scheme and an entire read or write cycle can be performed within the boundaries of a single clock cycle. The c50 operates at the
>boundaries.
>
>It looks like the 1610 does not suffer from this problem, but I have not gotten very
>far along in my analysis of this part. I haven't seriously looked at the 56156, yet.
>
>Thanks for any insight.
>-mike
>
>
>
I've experienced the same problem when I picked the c50. One thing I didn't
know at that time was that it has a lot of bugs (16 pages of problems and
workarounds to be exact). Another thing was that it takes 22 weeks to order
these damn chips!
I heard about the 56156 just recently. The fastest available version is
already faster than the c50 (30 vs 28.5 MIPS, if you can get the 35ns version
of c50). And the 40 MIPS version will be available next year. However, the
56156 is kinda new and there is not a lot of 3rd party support out there yet.
But I'd imagine this chip will get pretty hot because it is design to go
