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- Newsgroups: comp.arch
- Path: sparky!uunet!usc!wupost!rice!cliffc
- From: cliffc@rice.edu (Cliff Click)
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- In-Reply-To: gints@roadkill.esd.sgi.com's message of Thu, 30 Jul 1992 06:37:23 GMT
- Message-ID: <CLIFFC.92Jul30090928@antigone.rice.edu>
- Sender: news@rice.edu (News)
- Organization: Center for Research on Parallel Computations
- References: <55117@mentor.cc.purdue.edu> <id.RKUR.GFF@ferranti.com>
- <55294@mentor.cc.purdue.edu> <id.GQWR.83D@ferranti.com>
- <1992Jul30.063723.21080@odin.corp.sgi.com>
- Date: Thu, 30 Jul 1992 15:09:28 GMT
- Lines: 16
-
- In article <1992Jul30.063723.21080@odin.corp.sgi.com> gints@roadkill.esd.sgi.com (Gints Klimanis) writes:
- > Simple things like the tiny 8K instruction and data
- > caches really put limits on what you can run at the pipeline rate. The
- > 16 floating point registers for mips2 chips imposes severe limits on all
- > sorts filter implementations.
-
- Block for cache & register size; do scalar renaming. Does mongo good things
- to most small number-crunching inner loops. References are following via
- e-mail.
-
- Cliff
- cliffc@cs.rice.edu
-
- --
- The Sparc ABI has the most brain-damaged calling convention I've ever seen.
- Cliff Click (cliffc@cs.rice.edu) | Disclaimer: My lawyer made me say it.
-