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- Newsgroups: comp.arch
- Path: sparky!uunet!elroy.jpl.nasa.gov!usc!snorkelwacker.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!jfc
- From: jfc@athena.mit.edu (John F Carr)
- Subject: Re: Scheduling in Shared Memory Multiprocessor Systems
- Message-ID: <1992Jul25.141516.9529@athena.mit.edu>
- Sender: news@athena.mit.edu (News system)
- Nntp-Posting-Host: achates.mit.edu
- Organization: Massachusetts Institute of Technology
- References: <1992Jul15.040528.16289@access.usask.ca> <GLEW.92Jul23215649@pdx007.intel.com> <1992Jul24.183213.9699@elroy.jpl.nasa.gov>
- Date: Sat, 25 Jul 1992 14:15:16 GMT
- Lines: 15
-
- In article <1992Jul24.183213.9699@elroy.jpl.nasa.gov>
- david@elroy.jpl.nasa.gov (David Robinson) writes:
-
- >Isn't this an artifact of the Vax architecture having 32 hardware
- >queues and instructions to manipulate them? Have most BSD vendors
- >kept this structure or gone with something radically different?
-
- The VAX has queue management instructions and a find-first-bit
- instruction that scans 32 bits.
-
- The BSD port to the IBM RT used 16 run queues, because the RT
- find-first-bit instruction only scans 16 bits.
-
- --
- John Carr (jfc@athena.mit.edu)
-