NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/comp/arch/8290

Text File | 1992-07-25 | 1.8 KB | 35 lines

Newsgroups: comp.arch
Path: sparky!uunet!elroy.jpl.nasa.gov!ames!sgi!fido!zola!zuni!tenno.boston.sgi.com!tarolli
From: [e-mail] (Gary Tarolli)
Subject: Re: CISC Microcode (was Re: RISC Mainframe)
Message-ID: <[e-mail]>
Sender: [e-mail] (Net News)
Organization: Silicon Graphics, Inc.
References: <[e-mail]> <[e-mail]> <[e-mail]> <[e-mail]>
Date: Fri, 24 Jul 92 18:46:36 GMT
Lines: 23

In article <[e-mail]>, [e-mail] (Vadim Antonov) writes:
|> Did anybody thought that bcopy has nothing to do with the central processor?
|> I'd prefer to have a machine which thinks of it as of a pair of DMA-s.
some people think DMA is a dirty word....

|> It makes the whole system more "consistent" from the OS point of view.
|> There is no need to pump unchanged words through all those CPU
|> data caches effectively flushing them.
how do you then keep your data caches consistent with memory (in case some
of the bcopy's destination bytes were in the cache)?  If you flush or invalidate
your data cache, its not any different than pumping those words thru the cache.

|> The additional circuits are trivial but allow to keep the CPU simplier.
when one throws in all the non-simple complexities of alignment, direction,
and sometimes stride (used more for framebuffer operations than memory),
things become non-trivial real fast.  In fact, sometimes, they are complex
enough that its difficult to ever get DMA working correctly or more efficiently
than load/stores.
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