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  1. Path: sparky!uunet!elroy.jpl.nasa.gov!sdd.hp.com!think.com!news!jcallen
  2. From: jcallen@marley.think.com (Jerry Callen)
  3. Newsgroups: comp.arch
  4. Subject: Re: CISC Microcode (was Re: RISC Mainframe)
  5. Date: 24 Jul 92 13:21:52
  6. Organization: Thinking Machines Corporation, Cambridge MA, USA
  7. Lines: 21
  8. Message-ID: <JCALLEN.92Jul24132152@marley.think.com>
  9. References: <9207081402.AA25575@ucbvax.Berkeley.EDU>
  10.     <GLEW.92Jul12214745@pdx117.intel.com> <BrE09F.4JK@metaflow.com>
  11.     <1992Jul15.163217.434@urbana.mcd.mot.com> <BrM813.Du5@zoo.toronto.edu>
  12.     <GLEW.92Jul23184629@pdx007.intel.com>
  13. NNTP-Posting-Host: marley.think.com
  14. In-reply-to: glew@pdx007.intel.com's message of Fri, 24 Jul 1992 02:46:29 GMT
  15.  
  16. In article <GLEW.92Jul23184629@pdx007.intel.com> glew@pdx007.intel.com (Andy Glew) writes:
  17.  
  18.    By the way: creating virtual address aliases with different cache
  19.    properties is a recipe for a complicated, expensive, and lower
  20.    performance than it should be multilevel cache system.
  21.  
  22. How so? Since the R4000 uses a completely separate bus for the
  23. secondary cache, I don't see the complication. Uncached access
  24. go straight to the main memory bus; otherwise the usual cache
  25. lookup takes place. What am I missing?
  26.  
  27. -- Jerry Callen
  28.    jcallen@world.std.com           (preferred)
  29.    jcallen@think.com               (OK, too)
  30.    {uunet,harvard}!think!jcallen   (if you must)
  31.  
  32. --
  33. -- Jerry Callen
  34.    jcallen@world.std.com           (preferred)
  35.    jcallen@think.com               (OK, too)
  36.    {uunet,harvard}!think!jcallen   (if you must)
  37.