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- Newsgroups: comp.arch
- Path: sparky!uunet!pgroup!lfm
- From: lfm@pgroup.com (Larry Meadows)
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- Message-ID: <Brw95I.3ot@pgroup.com>
- Date: Fri, 24 Jul 1992 12:53:42 GMT
- References: <2369@nic.cerf.net> <BruruF.2E4@zoo.toronto.edu> <2373@nic.cerf.net>
- Organization: The Portland Group, Portland, OR
- Lines: 8
-
- In article <2373@nic.cerf.net> davsmith@nic.cerf.net (David Smith) writes:
- >Among current microprocessors I don't know of any that are able to
- >issue multiple data fetches.
-
- The i860 can issue 3, that is, the bus can handle 3 pipelined accesses.
- --
- Larry Meadows The Portland Group
- lfm@pgroup.com
-