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- Path: sparky!uunet!olivea!veritas!amdcad!dvorak.amd.com!electron!scott
- From: scott@electron.amd.com (Scott McMahon)
- Newsgroups: comp.arch
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- Keywords: interleaved memory systems, processor support
- Message-ID: <1992Jul24.045944.28448@dvorak.amd.com>
- Date: 24 Jul 92 04:59:44 GMT
- References: <2369@nic.cerf.net> <BruruF.2E4@zoo.toronto.edu> <2373@nic.cerf.net>
- Sender: usenet@dvorak.amd.com (Usenet News)
- Organization: Advanced Micro Devices, Austin TX.
- Lines: 56
-
- In article <2373@nic.cerf.net> davsmith@nic.cerf.net (David Smith) writes:
- | In article <BruruF.2E4@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes:
- | >Uh, you are very much behind the times. Few modern CPUs will block waiting
- | >for a memory access unless/until they actually need the data. Admittedly,
- | >a lot of them can't initiate another memory access meanwhile -- or at
- | >least, another data access -- but some can, and buses that support multiple
- | >simultaneous memory transactions are old news.
- |
- | Sigh...The dangers of simplifying for clarity. I didn't feel like getting
- | into a long discussion of register scoreboarding and so forth. However,
- | if it can't initiate another fetch then as far as the memory system is
- | concerned it's hanging on the first one. That's the critical issue for a
- | using an interleaved memory system.
-
- The Am29030 and Am29035 microprocessors support a feature called Early
- Addressing, which is similar to what you describe (I certainly think
- it is a good step in the right direction).
-
- During burst transfers (instruction fetching, or load/store multiple
- operations) the processor is capable of providing addresses
- independent of the memory system's transfer acknowledge (RDY). Here is
- how how it works (an instruction fetch example will be given - the
- same applies for data accesses):
-
- 1. The processor drives the REQ (REQuest), A(31:0) (Address), BURST
- (BURST mode access), and other signals indicating an instruction
- fetch is beginning.
-
- 2. Before/during the return of the first instruction, the memory
- system asserts the ERLYA (EaRLY Address) input. This causes the
- processor to drive the address+8 on the next cycle. The only
- other condition for entering the early address mode is that the
- initial address be quad-word aligned (A(3:0) = 0). This is
- *ALWAYS* the case at the beginning of an instruction fetch in the
- Am29030/35. For data accesses not starting at a quad-word aligned
- address, the processor increments addresses by 4 until the
- alignment criteria is met.
-
- 3. The memory system now controls the incrementing of the address
- bus independent of data transfer. When it returns an instruction
- or data item it asserts RDY; when it wants the next address it
- asserts ERLYA.
-
- This feature was added to assist designers in interleaved memory
- systems. The intent is to provide all even-bank addresses as the
- memory system requires.
-
- A two-way interleaved system is pretty trivial to design with this
- feature.
-
- -Scott
- --
- Scott McMahon
- Advanced Processor Development, Am29030 Team
- Advanced Micro Devices
- scott@amd.com
-