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- From: gkc@freddie.udev.cdc.com (gordon k chace x2367)
- Newsgroups: comp.arch
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- Message-ID: <45565@shamash.cdc.com>
- Date: 23 Jul 92 14:16:07 GMT
- References: <BrM8Gv.E3r@zoo.toronto.edu> <ADAMS.92Jul21011202@PDV2.pdv2.fmr.maschinenbau.th-darmstadt.de> <Brsx7o.G69@zoo.toronto.edu> <2369@nic.cerf.net>
- Sender: usenet@shamash.cdc.com
- Lines: 18
-
- In article <2369@nic.cerf.net>, davsmith@nic.cerf.net (David Smith) writes:
- |> All CPUs I have seen to date (not every CPU by any means - if you know
- |> of counter examples, please post) cannot do asynchronous address
- |> generation. When they request a word of memory they want it *NOW* or
- |> within a cycle or two and will block until it arrives. This makes it
- |> impossible to get full bandwidth out of an interleaved memory system if
- |> the cache is removed.
-
- Counterexamples from many years ago: CDC 6600, 7600 and derivatives thereof.
-
- My friends at the two Cray companies will probably include their systems
- as additional counterexamples.
-
- --
- Gordon K. Chace
- Control Data Systems, Inc. phone (612) 482-6524 fax 482-2791
- email gkc@udev.cdc.com
- RISC: Really Invented on the Sixty-six-hundred by CDC
-