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- Path: sparky!uunet!caen!hellgate.utah.edu!cc.usu.edu!ivie
- From: ivie@cc.usu.edu (CP/M lives!)
- Newsgroups: comp.arch
- Subject: Re: CISC Microcode (was Re: RISC Mainframe)
- Message-ID: <1992Jul22.163956.57436@cc.usu.edu>
- Date: 22 Jul 92 16:39:56 MDT
- References: <13v85hINN2og@rodan.UU.NET> <GLEW.92Jul14234349@pdx007.intel.com> <Brsx7o.G69@zoo.toronto.edu>
- Organization: Utah State University
- Lines: 8
-
- In article <Brsx7o.G69@zoo.toronto.edu>, henry@zoo.toronto.edu (Henry Spencer) writes:
- > Item 3 can still be
- > an issue, particularly on old architectures with clunky interrupt handling,
-
- What do you mean by "clunky interrupt handling"?
-
- Roger Ivie
- ivie@cc.usu.edu
-