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- From: lindsay+@cs.cmu.edu (Donald Lindsay)
- Newsgroups: comp.arch
- Subject: Re: 1000 MHz
- Keywords: decwrl BIPS-1
- Message-ID: <1992Jul22.170454.139562@cs.cmu.edu>
- Date: 22 Jul 92 17:04:54 GMT
- Article-I.D.: cs.1992Jul22.170454.139562
- References: <1992Jul18.153606.217022@cs.cmu.edu> <1992Jul19.195304.27021@athena.mit.edu>
- Organization: School of Computer Science, Carnegie Mellon
- Lines: 35
- Nntp-Posting-Host: gandalf.cs.cmu.edu
-
- solman@athena.mit.edu (Jason W Solinsky) writes:
- >|> DECWRL has the following project:
- >|> "BIPS-1"
- >|> 1,000 MHz
- >|> 8 KB first level onchip cache, bipolar, 1 ns
- >|> 32 KB second level onchip cache, BiCMOS, 3 ns
- >|> 130 watts
- >
- >I believe I was recently told that an ENTIRE one of those new IBM ES/9000
- >uses around 1500 watts. I think that it would take some pretty smart
- >engineering to make it economical to cool the little toaster.
-
- Smart, yes, but the engineering is mostly in hand. DECWRL's tech
- report 92/1 describes putting a 150 W ECL chip, with 348 signal pins,
- into a socketed plastic package (a PPGA). Their estimate was that the
- non-volume-production price of the packaging would be $300, counting
- the price of the two 6 cm fans attached to the 12 cm cooling tower.
- They claim it would operate (quietly) inside a standard desk-top box.
-
- I'm not sure why people think that 130 watts would be hard to cool.
- When there's only one such chip in a system, the only challenge is to
- do it cheaply and compactly and quietly. When a machine contains
- (say) 4 GB of ECL SRAM, then the heat isn't even in one place, and
- there might be 10 KW or even 100 KW to dispose of - machine room
- time.
-
- From the mail of the last few days, a correction: the first level
- cache is also BiCMOS. A true ECL design took too much silicon.
-
-
-
-
-
- --
- Don D.C.Lindsay Carnegie Mellon Computer Science
-