NetNews Usenet Archive 1992 #16/NN_1992_16.iso/spool/biz/comp/software/105

Internet Message Format | 1992-07-23 | 5.5 KB

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From: [e-mail] (Mitch Wyle)
Newsgroups: biz.comp.software
Subject: (June 8) SYNOPSYS INTRODUCES BREAKTHROUGH IN SYNTHESIS TECHNOLOGY
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Date: 24 Jul 92 02:27:26 GMT
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Organization: Synopsys Inc.
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New generation of synthesis brings timing-driven sequential optimization
to a broad range of design styles.

ANAHEIM, Calif.  June 8, 1992  Synopsys Inc. today introduced Version
3.0 of its synthesis tools at the 29th Design Automation Conference in
Anaheim, Calif.  Version 3.0 of the Design Compiler and HDL Compiler
synthesis products, cornerstones of the company's high level design
automation product line, brings breakthrough technology in electronic
circuit timing optimization to the world's largest installed base
of synthesis users.  "Four years of Synopsys customer experience has
confirmed that quality of results  as defined by area, performance, and
testability  is critical to designers," said Penny Herscher, director
of Synopsys product marketing.

"Synopsys determined that the next major step in synthesis was to
move into timing-driven sequential optimization.  To make this move,
we focused on the timing verification technology that drives timing
optimization and leveraged Synopsys' original research.  By re-writing
the core of the timing optimizer, we made the breakthrough to timing
driven sequential optimization."  Synopsys' breakthrough technology,
a fast path-based timing verifier, enables designers to optimize complex
sequential circuits for performance by verifying the point-to-point timing
very quickly within the core timing optimizer.  Designers can now apply
synthesis to multi-clock, multi-cycle, multi-phase designs (common in
communications products); and further optimize the register transfer level
(RTL) description of the design by re-positioning registers to improve
design performance (a common practice in the design of high-performance
computing products).

Version 3.0 adds timing-driven sequential optimization to both the Design
Compiler and Test Compiler families of synthesis products.  The Test
Compiler family, which includes full scan, partial scan, and boundary
scan (JTAG) design for test and automatic test pattern generation,
was introduced in May 1992 at the Custom Integrated Circuits Conference.

Benefits of the New Technology

Synopsys' new timing optimization tools derive extra performance
in latch-based designs by taking advantage of certain properties of
latches that enable the tools to "borrow time" between logic stages.
Automatic time borrowing allows latch-based designs, typically used
for high performance products, to be optimized for faster clock speeds.
The technique is considered difficult in manual design.

One of the challenges that designers face in working with more than
one single-phase clock is the creation of timing constraints  or timing
relationships  for synthesis.  In Version 3.0, the timing constraints
are derived automatically, thereby greatly simplifying the timing
optimization and ensuring that the right constraints are used to drive
the optimization.

Quality of Results is Key

Two new RTL optimization techniques are expected to offer even greater
improvements in the quality of circuits designed with Synopsys synthesis
tools:  timing-driven arithmetic optimization and pipeline re-timing.
These techniques expand the capabilities of the HDL Compiler family to (1)
optimize arithmetic expressions based on performance requirements and,
(2) increase the clock speed of high performance pipelined designs.
After a year of development effort, early results from beta software
show improvements in performance, area, and testability of all designs
synthesized with Version 3.0.  Each previous version of Synopsys'
synthesis tools has increased design performance an average of greater
than ten percent.  Version 3.0 is expected to offer even greater
performance improvements for complex clocking and high performance
design styles.


Compatibility

Version 3.0 can be used with all existing ASIC and FPGA vendor libraries
and all designs developed with previous versions of Synopsys' HLDA tools
Design Compiler family, HDL Compiler family, Test Compiler family,
VHDL System Simulator, and Design Analyzer).  This enables customers
to retain their investment in previous tools, libraries, design work,
and training.  Over 100 certified libraries are available from more than
30 ASIC and FPGA vendors.

Price and Availability

Version 3.0 is currently expected to be available at the end of
calendar year 1992.  U.S. pricing is currently expected to start
at $45,000.  Customers under maintenance and support agreements will
automatically receive the new version.  Synopsys Inc. develops, markets,
and supports high level design automation (HLDA) software for designers
of integrated circuits and electronic systems.  The company currently
offers a comprehensive set of synthesis, simulation, and test tools,
which are supported on most widely used UNIX workstations.

VHDL System Simulator, HDL Compiler, Design Compiler, Test Compiler,
and Design Analyzer are trademarks of Synopsys Inc..  Synopsys is a
registered trademark of Synopsys Inc.  All other brands or products
are trademarks or registered trademarks of their respective holders and
should be treated as such.

For more information, contact:

Lois DuBois                    [e-mail]
Synopsys Inc                   [phone]
700 E. Middlefield Rd.         [phone] (fax)
Mountain View, CA  94043-4033  [phone] x4255