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- ACCEL P-CAD PCB Version 12.00 Routing Log File
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- ============================================================================
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- Input file: C:\ACCEL\DEMO\DEMO1_P.PCB
- Output file: C:\ACCEL\DEMO\RDEMO1_P.PCB
- Strategy file: C:\ACCEL\DEMO\DEMO1_P.STR
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- All dimensions are in mils unless stated.
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- Routed by: PRO Route
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- Start time: 08:00:29 24-Jan-96
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- Free memory: 708608
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- Strategy selections:
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- Routing grid: 25.0*
- Via grid: 25.0*
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- Copper sharing: Vias and lines
- Checkpoint interval: 120 (minutes)
- Diagonal routing: Yes
- Simultaneous class routing: No
- Rip-up preroutes: Yes
- Force manufacturing pass: No
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- Iterative passes: 5
- Manufacturing passes: 2
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- * Selected by router.
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- Layer selections:
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- Signal Bias or Plane Clearances
- Layer Selection Net Name P-P P-L L-L V-P V-L V-V
- ------ ---------- ---------------- ----- ----- ----- ----- ----- -----
- Top Hor 12 12 12 12 12 12
- Bottom Ver 12 12 12 12 12 12
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- * Selected by router.
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- Net classes:
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- Net Max
- Class Width Via Padstack Prio Layer Vias Notes
- ------- ----- -------------------- ---- ------ ---- -----
- Default 12.0 (Default) 1 All *
- ---------------------------------------------------------
- Notes: F = Fixed, do not ripup.
- N = Do not route.
- W = Use wide pass.
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- Scheduled pass selection:
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- 24-Jan-96 08:00 Page 1
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- ACCEL P-CAD PCB Version 12.00 Routing Log File
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- Pass Net Classes
- Num Pass Name DFT
- ---- ------------------ -----------
- 1* Memory x
- 2* Initial x
- 3* Comprehensive x
- 4* Exhaustive x
- 5* Iterative x
- 6* Iterative x
- 7* Iterative x
- 8* Iterative x
- 9* Iterative x
- 10* Manufacturing x
- 11* Manufacturing x
- 12* Final mfg x
- 13* Final mfg x
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- * Selected by router.
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- 24-Jan-96 08:00 Page 2
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- ACCEL P-CAD PCB Version 12.00 Routing Log File
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- ============================================================================
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- 138 total connections on the board.
- 36 pre-routed connections.
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- Pass Performance Summary:
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Memory Pass Num: 1 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 52
- Completed 43 ( 82%) 79 ( 57%)
- Not completed 9 ( 17%) 59
- Vias 0 ( 0%) 4
- Copper length (inches) 35.2493 ( 54%) 64.0962
- Elapsed time 0:00:06 ( 37%) 0:00:16
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Initial Pass Num: 2 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 59
- Completed 46 ( 77%) 125 ( 90%)
- Not completed 13 ( 22%) 13
- Vias 34 ( 89%) 38
- Copper length (inches) 72.5272 ( 53%) 136.6233
- Elapsed time 0:00:17 ( 48%) 0:00:35
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Comprehensive Pass Num: 3 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 13
- Completed 10 ( 76%) 135 ( 97%)
- Not completed 3 ( 23%) 3
- Vias 16 ( 29%) 54
- Copper length (inches) 25.1284 ( 15%) 161.7517
- Elapsed time 0:00:11 ( 23%) 0:00:47
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Exhaustive Pass Num: 4 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 3
- Completed 3 (100%) 138 (100%)
- Not completed 0 ( 0%) 0
- Vias 9 ( 14%) 63
- Copper length (inches) 12.3728 ( 7%) 174.1245
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- 24-Jan-96 08:01 Page 3
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- ACCEL P-CAD PCB Version 12.00 Routing Log File
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- ============================================================================
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- Elapsed time 0:00:04 ( 7%) 0:00:53
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Manufacturing Pass Num: 10 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 0
- Completed 0 (100%) 138 (100%)
- Not completed 0 (100%) 0
- Vias -14 (-22%) 49
- Copper length (inches) -6.6424 ( -3%) 167.4821
- Elapsed time 0:00:16 ( 22%) 0:01:11
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Manufacturing Pass Num: 11 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 0
- Completed 0 (100%) 138 (100%)
- Not completed 0 (100%) 0
- Vias -6 (-12%) 43
- Copper length (inches) -0.9761 ( 0%) 166.5061
- Elapsed time 0:00:17 ( 19%) 0:01:29
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Final mfg Pass Num: 12 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 0
- Completed 0 (100%) 138 (100%)
- Not completed 0 (100%) 0
- Vias -1 ( -2%) 42
- Copper length (inches) -0.2950 ( 0%) 166.2111
- Elapsed time 0:00:16 ( 14%) 0:01:47
- -------------------------------------------------
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- Net class: Default Width: 12.0mil Via Padstack: (Default)
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- Final mfg Pass Num: 13 Overall
- ---------------------- ---------------- ---------
- Routes 138
- Scheduled 0
- Completed 0 (100%) 138 (100%)
- Not completed 0 (100%) 0
- Vias 0 ( 0%) 42
- Copper length (inches) -0.0000 ( 0%) 166.2111
- Elapsed time 0:00:16 ( 12%) 0:02:05
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- 24-Jan-96 08:02 Page 4
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- ACCEL P-CAD PCB Version 12.00 Routing Log File
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- ============================================================================
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- -------------------------------------------------
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- Final statistics:
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- Board:
- Physical dimensions (inches): 5.135 by 2.510
- Routing area (square inches): 12.889
- Total pads in file: 218
- Equivalent 16-pin ICs (EICs): 13.625
- Density (square inches per EIC): 0.946
- Routing performance:
- Total routed length (inches): 166.211
- Vias total: 42 ( 19% of total pads)
- Vias added: 38 ( 90% of total vias)
- Routed connections (this run): 102
- Routed connections (total): 138 (100%)
- Unrouted connections (total): 0 ( 0%)
- Total routing time: 0:02:06
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- Start time: 08:00:29 24-Jan-96
- Completion time: 08:02:35 24-Jan-96
- Free memory: 207204
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- End of log file.
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