PC World Komputer 1996 September

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.C1. DEVICE USAGE NOTES B This appendix lists the programmable logic devices (PLDs) that require special attention when being used with CUPL and CSIM. Many of these devices are not available in the STARTER KIT but they are available in the the full package. Device Mnemonic: CY7C330 See CY7C330 Application Notes for a detailed explanation of this device and its features. Device Mnemonic: EP300, P18CV8 1. The registered, internal combinatorial and I/O feedback paths can be selected by using the .DFB, .INT and .i.Extensions .IO extensions respectively. If the feedback type is the same as the output (registered feedback for registered output), a feedback extension ".IO" is required. Device Mnemonic: EP312, EP324 1. These devices support allocation of P-terms between adjacent macrocells. This means, unused P-terms may be borrowed by a macrocell from each of its adjacent macrocells. CUPL automatically performs this borrowing of terms whenever a design requires more than eight terms per macrocell if the adjacent macrocells use less than five P-terms. 2. This device has T registers and the polarity is placed before the register. When the pin is defined as active low, this has the effect of toggling the register when the signal approaching the register is a binary 0 because the signal is inverted before it reaches the register. This situation will cause the design to behave differently rather than just exhibiting a change in the polarity of the output signals. 3. The TURBO bit is supported. To set the TURBO bit, use the FUSE statement in the .PLD file for the 312 and 324 respectively as follows: FUSE(13712, 1); FUSE(47492 , 1); Device Mnemonic: EP320 1. Miser bits: 2912-2913 Turbo bits: 2914-2915 Device Mnemonic: EP600, EP900 1. Support for registered mode of the macrocell consists only of D-type and T-type flip-flops. J-K and S-R flip-flops are not supported because they don't physically exist in the device. They must be emulated with exclusive-or equations. 2. The D-type registered, T-type registered, and I/O feedback paths can be selected by using the .DFB, .TFB and .IO extensions respectively. If the feedback type is the same as the output (D-type registered feedback for D-type registered output), then a feedback extension is not required. 3. EP600/610 Turbo bits: 6480-6481 EP900/910 Turbo bits: 17400-17401 Device Mnemonic: EP1200/1210 1. Turbo bit: 15145 Device Mnemonic: EP1800/1810 1. Miser bits: 42480-42487 Turbo bits: 42488-42489 2. Please refer to the Application note on the EP1800. Device Mnemonic: F155,F157, F159, F179 1. Registers may be used as either D-type or JK-type, but not both (no dynamic conversion). 2. The output enable buffer for all registers is always controlled by pin 11 (pin 13 for F179). 3. The load control term for loading registers from the output pins) is not supported. 4. The product term that drives the register control buffer is fixed and may not be accessed to drive the complement array. Device Mnemonic: F501,F502 1. Both f501 and f502 contain NAND array architecture. The NAND gates must be defined as complement array nodes. 2. Although there is only one product term for each output pin in f501 and f502, multiple product term output can be implemented using DeMorgan algorithm and NAND node. For example, to implement the following logical function in f502: X = (a & b) # (c & d) # (e & f); Define as follows: Pin 19 = X; Pinnode 81 = !X1; Pinnode 82 = !X2; Pinnode 83 = !X3; X = !(!X1 & !X2 & !X3); X1.ca = a & b; X2.ca = c & d; X3.ca = e & f; Device Mnemonic: F506 1. The registered clock polarity is set by writing one .CKMUX expression for all registers used in the design. By default, the clock is treated as positive-edge triggered. Device Mnemonic: F507 1. The register and counter clock polarity are set by writing one .CKMUX expression for all registers and counter inputs used in the design. By default, the clock is treated as positive-edge triggered. 2. The built-in counter input nodes are defined using the NODE or PINNODE statements, and the .CNT extension. The counter clear and hold controls are defined using the NODE or PINNODE statements and writing either combinatorial or S-R registered expressions. 3. CSIM generates the counter inputs automatically, based on the counter control logic. Device Mnemonic: F16V8, F18V8Z, F20V8 1. These devices emulate two different PAL architectures with their flexible output macro configuration . If the F16V8, F18V8Z or F20V8 device mnemonic is used, the device parameters for the proper sub-mode are automatically selected according to the following: A. Registered Mode Specifying any output pin as registered invokes the registered mode (D). Specifying any output enable term for a nonregistered pin invokes the registered mode (D). Mnemonic: F16V8D F18V8ZD F20V8D B. Small Mode If neither of the above conditions are met, the device type defaults to the small mode (S). Mnemonic: F16V8S F18V8S F20V8S 2. Either the automatic selection mechanism or the device mnemonic for the specific sub-mode may be used. Device Mnemonic: G16V8,G20V8 1. These devices emulate three different PAL architectures with their flexible output macro configuration . If the G16V8 or G20V8 device mnemonic is used, the device parameters for the proper sub-mode are automatically selected according to the following: A. Medium Synchronous (Registered) Mode This mode is automatically chosen when the PLD source file has registered output. In the medium synchronous mode, specifying an output enable term for a registered output pin is not flagged as an error by the compiler or simulator. In this mode, the output enable control for registered pins is common to pin 11 (GAL16V8) or pin 13 (GAL20V8). Mnemonic: G16V8MS Input only Output only Input/Output 2, 3, 4, 12, 13, 14, 5, 6, 7, 15, 16, 17, 8, 9 18, 19 Pin 1 = common clock Pin 11 = common output enable Mnemonic: G20V8MS Input only Output only Input/Output 2, 3, 4, 15, 16, 17, 5, 6, 7, 18, 19, 20, 8, 9, 10, 21, 22 11, 14, 23 Pin 1 = common clock Pin 13 = common output enable B. Medium Asynchronous (Complex) Mode This mode is automatically chosen when the PLD source file has an output enable term for a non-registere d pin and/or. Mnemonic: G16V8MA Input only Output only Input/Output 1, 2, 3, 12, 19 13, 14, 15, 4, 5, 6, 16, 17, 18 7, 8, 9,11 Mnemonic: G20V8MA Input only Output only Input/Output 1, 2, 3, 15, 22 16, 17, 18, 4, 5, 6, 19, 20, 21 7, 8, 9, 10, 11, 13, 14, 23 C. Small (Simple) Mode (Default) If none of the above are met, the device type defaults to the small mode. In this mode, the Input/Output pins are configured as either Input Only or Output only (that is, no feedback can occur) . Mnemonic: G16V8S Input only Output only Input/Output 1, 2, 3, 15, 16 12, 13, 14, 4, 5, 6, 17, 18, 19 7, 8, 9,11 Mnemonic: G20V8S Input only Output only Input/Output 1, 2, 3, 18, 19 15, 16, 17, 4, 5, 6, 20, 21, 22 7, 8, 9, 10, 11, 13, 14, 23 2. Either the automatic selection mechanism or the device mnemonic for the specific sub-mode desired can be used. G20XV10 DEVICE NOTE THE G20XV10 can emulate the following devices in the corresponding modes: Device G20XV10 Mode Mnemonic P12L10 Input g20xv10i P20L10 Input g20xv10i P20X10 Feedback g20xv10f P20X8 Feedback g20xv10f P20x4 Feedback g20xv10f Each output can be configured as registered or combinatorial with either 3 pterms ORed together or 4 pterms XORed together as input. The following table shows how to obtain the different configurations of the Output Logic Macrocell (OLMC): OLMC Configuration Implementation in Design ------------------ ------------------------ Registered output XOR input, COE Default OR input, OE pterm Use OE extension Combinatorial output XOR input, COE Use OEMUX extension OR input, OE pterm Default If one would like to force CUPL to use a specific mode for the design, just use the mnemonic that represents that mode. If the G20XV10 device mnemonic is used, the device parameters for the proper sub-mode are automatically selected according to the following: INPUT MODE This mode is automatically chosen when the PLD source file has combinatorial output only. Device Mnemonic:g20xv10i Input Only Output Only Input/Output 2, 3, 4, 14, 23 15, 16, 17, 5, 6, 7, 18, 19, 20, 8, 9, 10, 21, 22 11 Pin 1 can be used both as a Synchronous Clock and an Input. Pin 13 can be used both as a Common Output Enable (COE) and an input. FEEDBACK MODE This mode is automatically chosen when the PLD source file has registered output. Device Mnemonic: g20xv10f Input Only Output Only Input/Output 2, 3, 4, 14, 15, 16, 5, 6, 7, 17, 18, 19, 8, 9, 10, 20, 21, 22, 11 23 Pin 1 is the Synchronous Clock. Pin 13 is the Common Output Enable (COE). Device Mnemonic: G6001 See GAL6001 Application Notes for a detailed explanation of this device and its features. 1. The output logic macrocell feedback paths can be selected as internal only, I/O only, or both, via the .INT and .IO extensions. If the feedback type is the same as the output (internal feedback for registered output), then a feedback extension is not required. 2. The output logic macrocells can be treated as buried register or combinatorial nodes, allowing the pins to be treated as inputs. The buried nodes must be defined in NODE or PINNODE statements and the input pins defined in PIN statements. 3. All input pins can be configured as registered or latched inputs via the .i.G6001:.DQ extension;.DQ and .LQ extensions, respectively. Each input pin in a group must be treated in the same manner. Device Mnemonic: MACH110,MACH210 See Chapter 5, FPGA and High Density PLDs. Device Mnemonic: P10P8V,P12P6V, P14P4V, P16P2V 1. The output macrocell for these devices is always configured for the OR path, utilizing double the product terms of a standard PAL. The default bypass path (lower power) and XOR path are not supported. Device Mnemonic: P16P8V, P16RP4V, P16RP6V,P16RP8V 1 . The output macrocell for these devices is always configured for the default bypass path. The OR path (double product terms at the expense of an output pin) and XOR path are not supported. Device Mnemonic:P20RA10 1. Combinatorial Output: As with any other device that can have combinatorial output, an extension is not needed to define an output to be combinatorial . When an output is defined to be combinatorial , CUPL will automatically set the AP and AR to 'b'1 enabling the register to be bypassed. 2. Registered Output: The 20RA10 has only one feedback path, the I/O feedback. When using registered output normally the feedback would come from the register, but in this device the feedback comes from the pin. If the feedback is needed the IO extension must be added to the variable name to use the pin feedback path. This follows the CUPL rules for when to use feedback extensions. 3. Programmable Preset and Reset: In each macrocell, two product lines are dedicated to asynchronous preset (AP) and asynchronous reset (AR). If the AP line is HIGH, the Q output of the register becomes a logic 1. If the AR line is HIGH, the Q output of the register becomes a logic 0. If both the AP and AR lines are HIGH, the flip-flop is bypassed and the output becomes combinatorial . The operation of AP and AR overrides the asynchronous clock (CK). 4. Three- State (OE) Outputs: The 20RA10 has a product term dedicated to local output control (OE) and also a global output control pin. The output is enabled if both the global output control pin is LOW and the local output control product term is HIGH. If the global output control pin is HIGH, all outputs will be disabled. If the local output control product t Device Mnemonic: P20X4,P20X8, P20X10 1. When writing logic equations for devices containing an XOR gate, the $ operator may not be included inside any parentheses that change the evaluation order of the expression. 2. When applying DeMorgan's Theorem to an equation involving the XOR gate, the expression written first is the one negated. Device Mnemonic: P22CV10,P22VP10, P23S8 1. The registered and I/O feedback paths can be selected by using the .DFB and .IO extensions respectively. If the feedback type is the same as the output (registered feedback for registered output), then a feedback extension is not required. Device Mnemonic: P29M16 1. The output feedback paths can be selected as registered only, latched only, I/O only, registered and I/O or latched and I/O via the .DFB, .LFB and .IO extensions. If the feedback type is the same as the output (registered feedback or registered feedback for registered output), then a feedback extension is not required. 2. The dual feedback outputs can be treated as buried register or latched nodes, allowing the pins to be treated as inputs. The buried nodes must be defined in NODE or PINNODE statements and the input pins defined in PIN statements. 3. The dual feedback outputs can be treated as registered or latched inputs, via the .i.P29M16:DQ extension;.DQ and .LQ extensions. 4. Individual clock control is set by writing a .CKMUX expression. By default, the clock control is set to clock/latch enable pin1, positive edge triggered. 5. Individual output enable control is set by writing either a .OEMUX expression for common control, or a .i.P29M16:OE extension;.OE expression for banked product term control. By default, the output enable control is set to common output enable pin 11. Device Mnemonic: P29MA16 1. The output feedback paths can be selected as registered only, latched only, I/O only, registered and I/O or latched and I/O via the .DFB, .LFB and .IO extensions. If the feedback type is the same as the output (registered feedback for registered output), then a feedback extension is not required. 2. The dual feedback outputs can be treated as buried register or latched nodes, allowing the pins to be treated as inputs. The buried nodes must be defined in NODE or PINNODE statements and the input pins defined in PIN statements. 3. The dual feedback outputs can be treated as registered or latched inputs via the .DQ and .LQ extensions. 4. Individual clock or latch enable control is set by writing either a .CKMUX expression for synchronous control or a .CK expression for asynchronous control. By default, the clock control is set to clock/latch enable pin 1, positive edge triggered. 5. Individual output enable control is set by writing either a .OEMUX expression or common control, or by a .OE expression for banked product term control. By default, the output enable control is set to common output enable pin 11. Device Mnemonic: P32VX10 1. Combinatorial outputs have active low polarity, whereas registered outputs have programmable polarity. 2. The output feedback paths can be selected as registered only, I/O only, or both, via the .DFB and .IO extensions. If the feedback type is the same as the output (registered feedback for registered output), then a feedback extension is not required. 3. The outputs can be treated as buried register nodes allowing the pins to be treated as inputs. The buried nodes must be defined in NODE or PINNODE statements and the input pins defined in PIN statements. Device Mnemonic: PLX448 1. The output feedback paths can be selected as internal only, I/O only, or both, via the .INT and .IO extensions. If the feedback type is the same as the output (internal feedback for registered output), then a feedback extension is not required. 2. The outputs can be treated as a buried register or combinatorial nodes, allowing the pins to be treated as inputs. The buried nodes must be defined in NODE or PINNODE statements and the input pins defined in PIN statements. 3. The 48mA output pins can be programmed to behave as open collector outputs, by writing .TEC expressions. Device Mnemonic: RA10P8,RA11P8, RA12P8 1. Active-HI chip enables are simulated as Active-LO. Device Mnemonic: V750 1. The output feedback paths can be selected as registered only, I/O only, or both, via the .DFB and .IO extensions. If the feedback type is the same as the output (registered feedback for registered output), then a feedback extension is not required. 2. The outputs can be treated as buried register nodes allowing the pins to be treated as inputs. The buried nodes must be defined in the NODE or PINNODE statements and the input pins defined in PIN statements. 3. When an output requires more product terms than its sum term provides, CUPL uses the sum term pairing capability to increase the number of available product terms. This will cause an incorrect fuse map to be generated if the associated buried register is also being used. 4. Shared product term bits: Pin 23 - S1: 14365 Pin 22 - S1: 14368 Pin 21 - S1: 14371 Pin 20 - S1: 14374 Pin 19 - S1: 14377 Pin 18 - S1: 14380 Pin 17 - S1: 14383 Pin 16 - S1: 14386 Pin 15 - S1: 14389 Pin 14 - S1: 14392 Device Mnemonic V2500 1. The output feedback paths can be selected as registered with I/O or as combinatorial. When a registered output is specified, the .IO extension is required for the I/O feedback. 2. The outputs can be treated as buried register nodes allowing the pins to be treated as inputs. The buried nodes must be defined in the NODE or PINNODE statements and the input pins defined in PIN statements. 3. When an output requires more product terms than its sum term provides, CUPL uses the sum term pairing capability to increase the number of available product terms. This will cause an incorrect fuse map to be generated if the associated buried register is also being used. 4. Shared product term bits: Pin29 - S0-S1: 71552-71553 Pin28 - S0-S1: 71556-71557 Pin27 - S0-S1: 71560-71561 Pin26 - S0-S1: 71564-71565 Pin25 - S0-S1: 71568-71569 Pin24 - S0-S1: 71572-71573 Pin11 - S0-S1: 71576-71577 Pin12 - S0-S1: 71580-71581 Pin13 - S0-S1: 71584-71585 Pin14 - S0-S1: 71588-71589 Pin15 - S0-S1: 71592-71593 Pin16 - S0-S1: 71596-71597 Pin31 - S0-S1: 71600-71601 Pin32 - S0-S1: 71604-71605 Pin33 - S0-S1: 71608-71609 Pin34 - S0-S1: 71612-71613 Pin35 - S0-S1: 71616-71617 Pin36 - S0-S1: 71620-71621 Pin 9 - S0-S1: 71624-71625 Pin 8 - S0-S1: 71628-71629 Pin 7 - S0-S1: 71632-71633 Pin 6 - S0-S1: 71636-71637 Pin 5 - S0-S1: 71640-71641 Pin 4 - S0-S1: 71644-71645 Device Mnemonic: PLD9000 This is an imaginary device designed to represent a generalized PLA. It is intended to be used for designs which are not targeted for any particular device. The device contains 100 pins, 45 inputs, 50 outputs, and 5 clocks. Each output has individual output enable control and can be configured in one of four modes.: combinatorial/active low, combinatorial/active high, D-registered/active low, or D-registered/active high. There are no power and ground pins. The pin organization is as follows: 1. Pin organization: Pin 1 - A common register clock input for output pins 51 - 100. Pin 2 - A secondary common register clock input for output pins 61 - 70. Pin 3 - A secondary common register clock input for output pins 71 - 80. Pin 4 - A secondary common register clock input for output pins 81 - 90. Pin 5 - A secondary common register clock input for output pins 91 - 100. Pins 6 - 50 - Input pins. Pins 51 - 100 Input-Output pins. 2. Banked clock control is set by writing .CKMUX expressions. By default the clock control is set to clock pin 1. 3. There are 200 product terms organized in a PLA format, so each is available to any output. Device Mnemonic: VIRTUAL DESIGNING WITH THE VIRTUAL DEVICE The virtual device allows the user to create digital designs for programmable logic without regard to the target architecture. The virtual device is not a device at all. It is simply a removal of the restrictions by CUPL, allowing the design to contain unlimited product terms and pins. With the virtual device, CUPL allows all register types to be used. The virtual device is useful for determining the resources needed to implement your design.(See virtual device design examples in Chapter U5.) OUTPUT Valid output files when using virtual are .DOC, .PLA, .PDS, .LST, and .MX. The following are not valid output file for virtual device: .JED, .HEX, and .ABS. DESIGNING STATE MACHINES When designing state machines with the virtual device, you must indicate the register type. CUPL will not default the state bits to any type of register. If a specific register type is not indicated, compilation will still be completed but the resulting equations will not represent a state machine design. The following examples illustrate state machine design with the virtual device. D REGISTERED SequenceD bits{ present 'b'0 default next 'b'1; present 'b'1 default next 'b'0; } T REGISTERED SequenceT bits{ present 'b'0 default next 'b'1; present 'b'1 default next 'b'0; } JK REGISTERED SequenceJK bits{ present 'b'0 default next 'b'1; present 'b'1 default next 'b'0; } RS REGISTERED SequenceRS bits{ present 'b'0 default next 'b'1; present 'b'1 default next 'b'0; } PIN NUMBERING When designing with the virtual device, pins do not have to be numbered but they do have to be declared. Use the normal pin declaration commands but leave out the pin numbers. If you do want to put pin numbers you are free to do so. Pin = OE; Pin = [Q2..0]; When pins are declared with CUPL, there is no distinction between input and output pins at the time of declaration. CUPL determines whether pins are input or output depending upon the equations. Therefore, it is necessary to use pins consistently. The compiler will generate an error if pins are not used consistently. PARTITIONING One of the main uses for the virtual device is for partitioning. Since no device restrictions are placed on a virtual design, the design can be as large as necessary. The documentation file created by the compiler is fed into the partitioner which can then split the logic among multiple devices. The virtual device must also be used when FINDPLD is going to be used. FINDPLD is a one device fitter similar to PLPartition which can find a single PLD for your design.(See Device Independent Design Flow in Chapter U1.) [Picture] Figure B-1. Using Virtual For Partitioning [Picture] Figure B-2. Using Virtual Device With FindPLD INTERFACING WITH OTHER TOOLS The virtual device is used to interface with other tools such as XILINX, PLUSTRAN and other FPGA vendor compilers and tools. The output files used vary for each interface. [Picture] Figure B-3. Using Virtual Device With Other Tools LIMITATIONS There are some actual limitations built into the virtual device. The total number of allowable product terms is 9999. The maximum pins is 200 and the maximum nodes is 200. POLARITY AND THE VIRTUAL DEVICE In devices with fixed inverting buffers, CUPL will automatically apply DeMorgan's theorem to active high equations to implement these equations in the active low pin. In devices that have programmable polarity, DeMorgan's theorem is not applied because the polarity bit can be blown to implement the desired logic. Normally CUPL examines the polarity defined in the pin statement, the polarity of the left side of the equation and the polarity on the right side of the equations to determine the polarity of the final equation. These will all produce the same results in a P22V10 device Pin 2 = A; Pin 2 = A; Pin 2 = A; Pin 3 = B; Pin 3 = B; Pin 3 = B; Pin 16 = !X; Pin 16 = X; Pin 16 = X; X = A & B; !X = A & B; X = !(A & B); In a virtual device, CUPL ignores the polarity defined in the pin statement. It only looks at the polarity in the equations. These will all produce the same results in a VIRTUAL device Pin = A; Pin = A; Pin = A; Pin = A; Pin = B; Pin = B; Pin = B; Pin = B; Pin = !X; Pin = X; Pin = X; Pin = !X; !X = A & B; !X = A & B; X = !(A & B); X = !(A & B); What this means is that you cannot simply change the pin statement if you want to invert the logic of an equation. The change has to be done in the equation itself.