OS/2 Shareware BBS: 11 Util/11-Util.zip/cachc105.zip/CACHECHK.INS

Text File | 1995-06-29 | 6KB | 118 lines

   Cache test (c) 1995 Graham C. Norris

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   This program is copyright. It is not public domain. You may freely use it but
   may not disassemble or modify it. By running the program you assume all
   responsibility for any adverse result arising. The program is not warranteed,
   guarenteed, or in any other way assured to produce the correct result. Use at
   your own risk.

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   This program is intended to determine how much memory cache is present in
   a system. It is also intended to determine whether the cache is write-back
   or write-through.

   Only cache sizes known (by me) to be used are tested. These are 1K, 8K, 16K,
   32K, 64K, 128K, 256K, 512K and 1M. A cache line size of 16 bytes is assumed.

   The reason this program was written was because of the discovery that at
   least one motherboard supplier has found a way of selling defective cache
   without it being noticable. The motherboard in question had what appeared to
   be 256K of 15-ns cache. Removing the "Removing this label will void the
   warranty" label showed that all the chips whose speed was visible were 15ns,
   but those which weren't were 20ns. Rip-off number one.

   When the cache was moved to another motherboard, it would not work. Half of
   it was found to be defective: it would not work on any motherboard, or in the
   first bank on the original motherboard. A different BIOS on the original
   motherboard showed 128K of cache: the original BIOS still reported 256K. Rip-
   off number two. Ripped-off twice in one purchase!

   Why write this for OS/2, not DOS? First, I am no archaeologist, second I need
   to work with up to 1M memory at a time. The program should be run from an
   OS/2 command line either after booting from a floppy, or Alt-F1,C under Warp.
   If any other threads are active the results will be wrong.

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   The program requires OS/2 2.0 or higher and is a non-PM application. It takes
   no parameters and generates about 40 lines of output. The results of the
   program may be piped to a file.

   On a fast system with at least 256K cache the test will take less than five
   minutes. If you disable all the cache even a fast Pentium will take about
   15 minutes to complete the test. A 20MHz 486 with all cache disabled could
   take an hour. A DX2-80 takes about 2.5 minutes, a DX2-50 about 5, both with
   write-back level two caching.

   In case you don't know what level one or level two caches are, level one
   cache (L1) is the on-chip cache found in 486 and Pentium processors. Level
   two cache (L2) is the extra cache found on a motherboard. L1 is 8K on most
   486 processors and L2 is frequently 256K. Pentiums have a split 8K data and
   8K instruction cache; this program only measures the data cache. There are
   variations such as the 1K cache on Cyrix 486SLC processors and 16K on Intel
   486DX4 processors. 386's (other than IBM's 386SLC's which have 16K) don't
   have on-board cache so any external cache is L1 cache and there is no L2.

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   If the program reports L3 cache then you either have an unusual system, or
   other threads are interfering with the results. The program will run in an
   OS/2 window, but will not give reliable results: it can usually tell if the
   cache is write-back or write-through even under these conditions.

   Normally the program cannot determine whether write-back caching is provided
   by L1 or L2 cache (or both). If you think (or know) you have write-back L1
   cache (for example an Intel DX4-100), you can tell if you also have L2 write
   back caching by using your BIOS settings to set the L1 (or internal) cache to
   write-through. If the program still reports write-back caching you either
   have write-back L2 cache or a defective BIOS which did not disable L1.

   Talking of defective BIOSes, some allow L1 (internal) cache to be disabled
   with L2 (external) enabled. This may result in both being disabled despite
   what the BIOS claims. Compare the results of the program with all cache
   disabled and with L1 disabled with L2 enabled to check this.

   -*-

   1.01 - changed tests to improve analysis on fast CPUs
   1.02 - new test strategy to improve analysis on all CPU types and to
      reduce test run times (complete tests on DX2-66 with all cache
      disabled now take less than 25 minutes). Results are displayed
      after tests are complete instead of between tests to reduce
      interference with tests. Piped standard output will now include just
      heading and results, progress messages still go to the screen
   1.03 - minor changes to tests with new algorithm for determining whether
      cache is write through or write back. Added a beep when it's done
   1.04 - changed to improve on defective compiler optimisations (it uses
      registers for the outer loop control variables of nested loops rather
      than the control variables of the inner loops, which isn't what I call
      optimisation). Added builtin switch to 43/50 lines and colour.
   1.05 - changed to minimise impact of external threads. You've heard much of
      pre-emptive and co-operative multitasking. Well, this adds a new
      flavour, un-co-operative multitasking. If you try to run this
      alongside anything else you'll get to see how well a few lines of
      code can take over your machine. Don't try to run any type of
      communication program or anything important alongside it. Comms.
      programs will drop data, others may timeout. Try running it in
      an OS/2 window with the analog OS/2 clock or Pulse next to it.
      The results will still usually be incorrect if run from under the
      WPS.

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   If you have any constructive comments I would like to hear them, especially
   if the test gives you a result you regard as incorrect. I reserve the right
   to ignore you however.

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   Graham C. Norris. [e-mail]

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   All names are trademarks of their respective owners.