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1993-09-29
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************************************************* 08/31/93
* *
* IBM Wide Area Connector Technical Reference *
* *
*************************************************
**************
* CONTENTS *
**************
Introduction ............................................1
Interface Description (Programmers Model) ...............1
I/O Block Description ...................................1
Micro Channel I/O Address Ranges Supported ..........2
ISA I/O Address Ranges Supported ....................4
I/O Registers .......................................4
Zilog IUSC Communications Chip Configuration ............5
IUSC Signal Assignments .............................5
IUSC PORT (Link Control Register) ...................5
Request To Send (RTS) = IUSC PORT7 ..................6
General Purpose Outputs = IUSC PORT6-4 ..............6
Remote Loop Back (RLOOP) = IUSC PORT 3 ..............6
Local Loop Back (LLOOP) = IUSC PORT 2 ...............6
DTE Ready (DTR) = IUSC PORT 1 .......................6
Clock Input = IUSC PORT0 ............................6
EIB Clock Control Pins (RxREQ and TxREQ) ............7
Clock Configuration Examples ............................7
RS-232, RS-422, V.35 Externally Clocked .............7
RS-232, RS-422, V.35, X.21 Internally Clocked .......8
X.21 Externally Clocked .............................8
X.21 Clock Echo .....................................8
Link Status Registers (Locations 14h and 16h) ...........9
EIB Identification = LSR Bits 4-7 ...................9
General-Purpose Inputs = LSR Bits 2-3 ...............9
Test Mode Select (TMODE) = LSR Bit 1 ...............10
Data Set Ready (DSR) = LSR Bit 0 ...................10
Memory Page Register (Location 1Ch) ....................10
Interrupt Active Indicator (ISA) = Bit 7 ...........10
Memory Parity Error Indicator = Bit 6 ..............10
Parity Check Enable/Disable = Bit 5 ................10
Memory Page Register = Bits 0-4 ....................11
ISA Memory Address Registers (MARL and MARH)............12
Memory Address Register High (MARH) (Location 1Eh) .12
Memory Address Register Low (MARL) (Location 1Fh) ..12
ISA Adapter Identification (Locations 18h - 1Ch) .......13
ISA Interrupt Identification/IUSC Reset (Location 1Dh) .13
Micro Channel POS Registers ............................14
Adapter ID (0EFCDh) ................................14
POS[0] - Memory Address LSB ........................14
POS[1] - I/O Address Selector ......................15
POS[2] - Memory Address MSB ........................15
POS[3] - Interrupt Level Selector ..................15
Programming Tips and Z16C32 Anomalies ..................17
Crossover Cable Diagrams ...............................19
X.21 Crossover Cable ...............................19
RS-232C/V.24 Crossover Cable .......................19
Hardware Shared Memory Specification Considerations ....20
MC-A Systems .......................................20
ISA Systems ........................................20
WAC Configuration Parameters ...........................21
Installation of More Than One WAC Adapter ..............24
(Page 1)
******************
* INTRODUCTION *
******************
The Wide Area Connector (WAC) integrates two Zilog Z16C32 IUSC (Integrated
Universal Serial Controller) devices with 128K bytes of on-card buffer memory.
Each ISUC chip provides a single-link, multi-protocol data communications
controller and a two-channel DMA controller (transmit and receive). The
electrical interface for each communication link is contained on an Electrical
Interface Board (EIB), which plugs into the main WAC board.
For detailed descriptions of the IUSC chip and its programming, refer to the
following documents:
Zilog Z16C32 Product Specification (DC-2600-00)
Zilog Z16C32 Technical Manual (DC-8292-01)
Zilog Z16C32 Errata Sheet (Date 1/30/92)
Zilog Z16C32 Electronic Programmer's Manual
The Micro Channel WAC employs the Chips & Technology P82C611 MicroCHIPS device
as its bus interface.
***********************************************
* INTERFACE DESCRIPTION (PROGRAMMERS MODEL) *
***********************************************
This section describes the WAC adapter hardware in terms of its
interface to PC software. An overview of the IUSC device is also
presented (refer to the appropriate Z16C32 literature from Zilog for
additional details).
The WAC utilizes a 32-byte block of the PC I/O address space and a block
(variable size) of the PC memory address space. Into the I/O block are mapped
the IUSC chips (taking 8 bytes each), two Link Status Registers (1 byte each),
and a memory page register (1 byte). The ISA card has seven additional
registers located in the 32-byte I/O block: Read-only identification strings
for card location (4 bytes) and hardware interrupt (1 byte), plus write/read
registers for locating and sizing the WACs shared memory (2 bytes).
A bank of shared memory (128K bytes) is included on the WAC adapter. This is
mapped into the PC memory space using one of five possible window sizes (8k,
16K, 32K, 64K, or 128K bytes). The memory page register allow the PC to access
the entire 128K bytes of on-card memory through the selected window size.
In addition to memory and I/O resources, the WAC uses a single ISA or
Micro Channel interrupt request (IRQ) lines.
***************************
* I/O Block Description *
***************************
The address of the 32-byte I/O block is established by a DIP switch setting
(ISA) or POS bits (Micro Channel). The ISA adapter supports 14 different I/O
address ranges. The Microchannel adapter supports 64 different I/O address
ranges. In both cases, the I/O address must start on a 32-byte boundary as
designated in the following tables:
(Page 2)
************************************************
* Micro Channel I/O Address Ranges Supported *
************************************************
(Binary)
Address (Hex) POS[1] POS[3]
==================================
0000h - 001Fh 00000xxxb xxxx0xxxb
0400h - 041Fh 00000xxxb xxxx1xxxb
0800h - 081Fh 00001xxxb xxxx0xxxb
0C00h - 0C1Fh 00001xxxb xxxx1xxxb
1000h - 101Fh 00010xxxb xxxx0xxxb
1400h - 141Fh 00010xxxb xxxx1xxxb
1800h - 181Fh 00011xxxb xxxx0xxxb
1C00h - 1C1Fh 00011xxxb xxxx1xxxb
2000h - 201Fh 00100xxxb xxxx0xxxb
2400h - 241Fh 00100xxxb xxxx1xxxb
2800h - 281Fh 00101xxxb xxxx0xxxb
2C00h - 2C1Fh 00101xxxb xxxx1xxxb
3000h - 301Fh 00110xxxb xxxx0xxxb
3400h - 341Fh 00110xxxb xxxx1xxxb
3800h - 381Fh 00111xxxb xxxx0xxxb
3C00h - 3C1Fh 00111xxxb xxxx1xxxb
(Binary)
Address (Hex) POS[1] POS[3]
==================================
4000h - 401Fh 01000xxxb xxxx0xxxb
4400h - 441Fh 01000xxxb xxxx1xxxb
4800h - 481Fh 01001xxxb xxxx0xxxb
4C00h - 4C1Fh 01001xxxb xxxx1xxxb
5000h - 501Fh 01010xxxb xxxx0xxxb
5400h - 541Fh 01010xxxb xxxx1xxxb
5800h - 581Fh 01011xxxb xxxx0xxxb
5C00h - 5C1Fh 01011xxxb xxxx1xxxb
6000h - 601Fh 01100xxxb xxxx0xxxb
6400h - 641Fh 01100xxxb xxxx1xxxb
6800h - 681Fh 01101xxxb xxxx0xxxb
6C00h - 6C1Fh 01101xxxb xxxx1xxxb
7000h - 701Fh 01110xxxb xxxx0xxxb
7400h - 741Fh 01110xxxb xxxx1xxxb
7800h - 781Fh 01111xxxb xxxx0xxxb
7C00h - 7C1Fh 01111xxxb xxxx1xxxb
(Page 3)
************************************************
* Micro Channel I/O Address Ranges Supported *
************************************************
(Binary)
Address (Hex) POS[1] POS[3]
==================================
8000h - 801Fh 10000xxxb xxxx0xxxb
8400h - 841Fh 10000xxxb xxxx1xxxb
8800h - 881Fh 10001xxxb xxxx0xxxb
8C00h - 8C1Fh 10001xxxb xxxx1xxxb
9000h - 901Fh 10010xxxb xxxx0xxxb
9400h - 941Fh 10010xxxb xxxx1xxxb
9800h - 981Fh 10011xxxb xxxx0xxxb
9C00h - 9C1Fh 10011xxxb xxxx1xxxb
A000h - A01Fh 10100xxxb xxxx0xxxb
A400h - A41Fh 10100xxxb xxxx1xxxb
A800h - A81Fh 10101xxxb xxxx0xxxb
AC00h - AC1Fh 10101xxxb xxxx1xxxb
B000h - B01Fh 10110xxxb xxxx0xxxb
B400h - B41Fh 10110xxxb xxxx1xxxb
B800h - B81Fh 10111xxxb xxxx0xxxb
BC00h - BC1Fh 10111xxxb xxxx1xxxb
(Binary)
Address (Hex) POS[1] POS[3]
==================================
C000h - C01Fh 11000xxxb xxxx0xxxb
C400h - C41Fh 11000xxxb xxxx1xxxb
C800h - C81Fh 11001xxxb xxxx0xxxb
CC00h - CC1Fh 11001xxxb xxxx1xxxb
D000h - D01Fh 11010xxxb xxxx0xxxb
D400h - D41Fh 11010xxxb xxxx1xxxb
D800h - D81Fh 11011xxxb xxxx0xxxb
DC00h - DC1Fh 11011xxxb xxxx1xxxb
E000h - E01Fh 11100xxxb xxxx0xxxb
E400h - E41Fh 11100xxxb xxxx1xxxb
E800h - E81Fh 11101xxxb xxxx0xxxb
EC00h - EC1Fh 11101xxxb xxxx1xxxb
F000h - F01Fh 11110xxxb xxxx0xxxb
F400h - F41Fh 11110xxxb xxxx1xxxb
F800h - F81Fh 11111xxxb xxxx0xxxb
FC00h - FC1Fh 11111xxxb xxxx1xxxb
(Page 4)
************************************
* ISA I/O Address Ranges Supported *
************************************
The I/O address range setting of the WAC adapter must not duplicate any other
adapter in the system. If further assistance is required to set the switch
positions, your local systems coordinator should be consulted.
Card Number Dip Switch
Address (Hex) (NOTE) 4 5 6 7
=================================================
0120 - 013F 15 ON ON ON ON
0140 - 015F 14 OFF ON ON ON
0180 - 019F 13 ON OFF ON ON
01A0 - 01BF 12 OFF OFF ON ON
0220 - 023F 11 ON ON OFF ON
0240 - 025F 10 OFF ON OFF ON
0280 - 029F 9 ON OFF OFF ON NOTE
0280 - 029F 8 OFF OFF OFF ON ----
0520 - 053F 7 ON ON ON OFF See WACPORTNUM in
0540 - 055F 6 OFF ON ON OFF WAC Configuration
0580 - 059F 5 ON OFF ON OFF Parameters section
05A0 - 05BF 4 OFF OFF ON OFF for details on the
0620 - 063F 3 ON ON OFF OFF card number
0640 - 065F 2 OFF ON OFF OFF
0680 - 069F 1 ON OFF OFF OFF
0680 - 069F 0 OFF OFF OFF OFF
The I/O address block contains the IUSC (communications, DMA, and Link Control
Register), Link Status Registers, and memory address and access control
registers. Locations of those devices within the I/O address block is shown
in the following table:
***************************************************************************
* Addr Device Register Function *
* ======================================================= *
* 00h IUSCa DCAR DMA Command/Address Register - Channel A *
* 02h IUSCa (Not Used) *
* 04h IUSCa CCAR Channel Command/Address Register - Channel A *
* 06h IUSCa RDR,TDR Receive and Transmit Data Registers - Channel A *
* 08h IUSCb DCAR DMA Command/Address Register - Channel B *
* 0Ah IUSCb (Not Used) *
* 0Ch IUSCb CCAR Channel Command/Address Register - Channel B *
* 0Eh IUSCb RDR,TDR Receive and Transmit Data Registers - Channel B *
* 10h (Reserved) *
* 11h (Reserved) *
* 12h (Reserved) *
* 14h LINK LSRa Link Status Register - Channel A *
* 15h (Reserved) *
* 16h LINK LSRb Link Status Register - Channel B *
* 17h (Reserved) *
* 18h ISA ISAID0 Read-Only, ASCII 'S' (053h) ISA-ONLY *
* 19h ISA ISAID1 Read-Only, ASCII 'C' (043h) ISA-ONLY *
* 1Ah ISA ISAID2 Read-Only, ASCII 'A' (041h) ISA-ONLY *
* 1Bh ISA ISAID3 Read-Only, ASCII '0' (030h) ISA-ONLY *
* 1Ch PAGE Memory Page Register, Parity Control *
* 1Dh ISA IRQID Read-Only ISA Interrupt Request Level ISA-ONLY *
* Write-Only ISA Hardware Reset *
* 1Eh ISA MARL Memory Address Register - LSB ISA-ONLY *
* 1Fh ISA MARH Memory Address Register - MSB ISA-ONLY *
***************************************************************************
(Page 5)
************************
* IUSC Configuration *
************************
The IUSC chip is a flexible, powerful device incorporating serial
communications and two DMA channels. In addition it supplies an 8-bit "Port",
with programmable bit-direction (input/output). That port is used for link
control functions, including RTS (Request-To-Send) and DTR (Data Terminal
Ready).
IUSC
PIN Name Function
========================================================
RxD RxD Serial Receive Data from EIB
TxD TxD Serial Transmit Data to EIB
/RxC RxC- Receive Clock from EIB
/TxC TxC- Transmit Clock from EIB or clock output to EIB.
/RxREQ ICLK Internal CLocKing Select. HIGH (1) enables the clock drivers
on the EIB. LOW (0) disables the clock drivers.
/TxREQ XCKS auXilliary ClocK Select. Selects the source of XCLK-, which
is used for two functions on RTS: (1) Negation of RTS at the
end of a transmit frame, and (2) RTS to CTS delay generation
on the X.21 EIB. LOW (0) connects XCLK- to the IUSC
/TxC pin; HIGH (1) connects XCLK- to the IUSC /RxC pin.
/DCD DCD- Data Carrier Detect from EIB. Normally used as an
auto-enable for the receive functions.
/CTS CTS- Clear To Send from EIB. Normally used as an auto-enable for
the transmit functions.
PORT7 RTS Request To Send output to EIB.
PORT6 LCR6 General-Purpose output to EIB.
PORT5 LCR5 General-Purpose output to EIB.
PORT4 LCR4 General-Purpose output to EIB.
PORT3 LCR3 General-Purpose output to EIB.
PORT2 LCR2 General-Purpose output to EIB.
PORT1 DTR Data Terminal Ready output to EIB.
PORT0 CLOCK Clock Input (14.7456 MHz)
****************************************
* IUSC PORT (Link Control Functions) *
****************************************
The IUSC PORT hardware provides several general-purpose I/O pins, used for the
link control functions as defined in the following paragraphs:
(Page 6)
************************************
* Request To Send (RTS) = PORT 7 *
************************************
RTS, when HIGH, enables logic on the WAC to assert the RTS output to the
EIB. The negation of the RTS bit causes the hardware to drop its RTS output.
Logic on the WAC will continue to assert RTS until the transmitter is seen in
a marking condition for 8 consecutive bit times).
****************************************
* General Purpose Outputs = PORT 6-4 *
****************************************
Port bits 6, 5, and 4 are inverted and connected to the EIB, but are not
currently used on any WAC EIBs.
***************************************
* Remote Loop Back (RLOOP) = PORT 3 *
***************************************
Setting PORT 3 to HIGH causes the RS-232 EIB to assert its REMOTE LOOP output
on the link. Not used for the V.35 or X.21/RS-422 EIBs.
**************************************
* Local Loop Back (LLOOP) = PORT 2 *
**************************************
Setting PORT 2 to HIGH causes the RS-232 EIB to assert its LOCAL LOOP output
on the link. Not used for the V.35 or X.21/RS-422 EIBs.
*****************************
* PORT1 = LCR Bit 1 (DTR) *
*****************************
Setting PORT 1 to HIGH to cause the RS-232, V.35, or X.21/RS-422 (RS-422 mode)
EIB to assert DTR on the link. For the X.21/RS-422 EIB in X.21 mode, setting
PORT 1 to HIGH causes the X.21 interface to enter the "DTE READY" state.
*************************
* PORT0 = CLOCK INPUT *
*************************
Bit 0 of the IUSC Port MUST be programmed as an input. It is driven with a
14.7456 MHz clock signal, which can be used for link clock generation.
(Page 7)
*****************************************
* EIB Clock Control (RxREQ and TxREQ) *
*****************************************
The IUSC /RxREQ and /TxREQ pins should be programmed by software to operate as
general-purpose outputs. /RxREQ is connected to ICLK, whereas /TxREQ is
connected to XCKS, which operate as follows:
ICLK=LOW External Clocking (Normal DTE Operation)
The IUSC TxC- pin should be programmed as an input, and the TCLK output to
the EIB is not active.
ICLK=HIGH Internal Clocking (WAC supplies clock)
The IUSC TxC- pin should be programmed as an output, which will be
buffered onto the EIB as signal TCLK-. With ICLK HIGH, the EIB buffers
the TCLK signal onto the appropriate clock lines.
XCKS=LOW
The XCLK- signal taken from IUSC TxC- pin (which is affected by the
setting of ICLK, as previously described).
XCKS=HIGH
The XCLK- signal taken from IUSC RxC- pin (which is always driven by
the EIB).
The XCLK- signal is used by the RTS-drop logic on WAC, and by the
RTS->CTS delay logic on the X.21 EIB.
****************************************************************
* Clocking Example: RS-232, V.35, RS-422 Externally Clocked *
****************************************************************
In this case, the WAC is operating as a DTE and expects transmit and receive
clocks to be provided by the attached DCE. Software programs the IUSC as
follows:
ICLK (/RxREQ) = LOW (External Clock Driver Disabled)
XCKS (/TxREQ) = LOW (Clock RTS logic with TxC-)
/TxC = Input
/RxC = Input
Transmit Clk = /TxC Pin
Receive Clk = /RxC Pin
(Page 8)
**********************************************************************
* Clocking Example: RS-232, RS-422, V,35, X.21 Internally Clocked *
**********************************************************************
In this case the WAC is expected to supply the clock for the communications
link. That clock is output from the /TxC pin of the IUSC (which is internally
connected to one of the IUSC baud-rate generators). Software programming of
the IUSC is as follows:
ICLK (/RxREQ) = HIGH (External Clock Receiver Disabled)
XCKS (/TxREQ) = LOW (Clock RTS logic with TxC-)
/TxC = Output
/RxC = Input
Transmit Clk = /TxC Pin
Receive Clk = /TxC Pin
************************************************
* Clocking Example: X.21 Externally Clocked *
************************************************
In this case the WAC expects to receive a single clock from the DCE (X.21
signal 'S'). This clock is used for both transmit and receive data.
Programming of the IUSC is as follows:
ICLK (/RxREQ) = LOW (External Clock Driver Disabled)
XCKS (/TxREQ) = HIGH (Clock RTS logic with RxC-)
/TxC = Input
/RxC = Input
Transmit Clk = /RxC Pin
Receive Clk = /RxC Pin
****************************************
* Clocking Example: X.21 Clock Echo *
****************************************
In this case the WAC receives a clock from the DCE on X.21 signal 'S', and
echo a clock back to the DCE on X.21 signal. Programming of the IUSC is as
follows:
ICLK (/RxREQ) = HIGH (External Clock Driver Enabled)
XCKS (/TxREQ) = HIGH (Clock RTS logic with RxC-)
/TxC = Output
/RxC = Input
Transmit Clk = /RxC Pin
Receive Clk = /RxC Pin
(Page 9)
**************************************************
* Link Status Registers (Locations 14h and 16h) *
**************************************************
The WAC provides two read-only 8-bit registers (one per link) to allow software
to read the EIB type and link status. The layout of each Link Status Register
is illustrated below:
***********************************************************
* LSR Bit Name Function *
* ====================================================== *
* 7 DCID3 MSB of EIB ID *
* 6 DCID2 : *
* 5 DCID1 : *
* 4 DCID0 LSB of EIB ID *
* 3 LSR3 General-purpose input from EIB *
* 2 LSR2 General-purpose input from EIB *
* 1 LSR1 RS-232 EIB: TEST MODE *
* X.21/RS-42 EIB: RxData *
* 0 LSR0 Data Set Ready (DSR) *
***********************************************************
***************************************
* EIB Identification = LSR Bits 4-7 *
***************************************
The EIB ID bits indicate the type of EIB installed. All LOW (0000) means that
no EIB is present. Three EIB types are defined, with the other codes reserved
for future EIB types:
******************************************************************
* LSR BIT *
* 7 6 5 4 EIB and Cable Type *
* ==================================== *
* 0 0 0 0 None Installed *
* 0 0 0 1 RS-232 *
* 0 0 1 0 V.35 *
* 0 1 0 0 X.21/RS-422, with X.21 (or no) cable installed. *
* 0 1 0 1 X.21/RS-422, with RS-422 cable installed *
* (others) Reserved for future EIB types. *
******************************************************************
*******************************************
* General Purpose Inputs = LSR Bits 2-3 *
*******************************************
Bits 2 and 3 of the Link Status Register are general-purpose inputs from the
EIB, and are not used on any currently-defined EIBs. These will always read
back low (0).
(Page 10)
*************************************
* Test Mode Indicator = LSR Bit 1 *
*************************************
For the RS-232 EIB, this bit is HIGH if the TEST INDICATOR is being asserted by
the attached DCE.
For the X.21/RS-422 EIB, this bit is connected to RxD (receive data), and is
used by diagnostic software in testing of the EIB.
LSR Bit 1 is not used by the V.35 EIB, and will always read back low (0).
**************************************
* Data Set Ready (DSR) = LSR Bit 0 *
**************************************
For the RS-232 and V.35 EIBs, this bit reads high (1) if the attached DCE
asserts DSR.
For the X.21/RS-422 EIB, in X.21 mode, the DSR bit is asserted when the
attached DCE presents a "DCE READY" state.
For the X.21/RS-422 EIB, in RS-422 mode, the DSR bit follows the state of DTR
(IUSC PORT Bit 1).
*****************************************
* Memory Page Register (Location 1Ch) *
*****************************************
The Memory Page Register establishes the upper-most addresses for the adapters
memory and controls whether or not parity is checked on memory reads. Bits 0
through 4 of this register allows the PC software to access all of the adapter
RAM through a memory 'window' in the PC memory address space. Bits 5 through 7
of this register have functions related to parity checking and interrupts:
***********************************************************************
* Bit Name Function *
* ========================================================= *
* 7 IRQACT- Read-Only (LOW => adapter has active IRQ) ISA ONLY *
* 6 ERROR Read-Only, HIGH => Parity Error Detected *
* 5 PTYEN Write-Read, HIGH => Parity Checking is Enabled *
***********************************************************************
(Page 11)
Bits 0 through 3 of the Memory Page Register provide the high-order memory
address for the WACs 128K bytes of RAM, as illustrated in the following tables:
(Note that Bit 4 of this register is spare, reserved for future use).
*********************************************************
* Page Size = 8K Bytes (POS[0] or MARL = xxx10001b) *
* Page Reg WAC Memory Addresses Accessible by PC *
* ==================================================== *
* x0h 00000h through 01FFFh *
* x1h 02000h through 03FFFh *
* x2h 04000h through 05FFFh *
* x3h 06000h through 07FFFh *
* : : *
* xEh 1C000h through 1DFFFh *
* xFh 1E000h through 1FFFFh *
*********************************************************
*********************************************************
* Page Size = 16K Bytes (POS[0] or MARL = xxx10011b) *
* Page Reg WAC Memory Addresses Accessible by PC *
* ==================================================== *
* x0h 00000h through 03FFFh *
* x1h 04000h through 07FFFh *
* x2h 08000h through 0BFFFh *
* x3h 0C000h through 0FFFFh *
* : : *
* x6h 18000h through 1BFFFh *
* x7h 1C000h through 1FFFFh *
*********************************************************
*********************************************************
* Page Size = 32K Bytes (POS[0] or MARL = xxx10101b) *
* Page Reg WAC Memory Addresses Accessible by PC *
* ==================================================== *
* x0h 00000h through 07FFFh *
* x1h 08000h through 0FFFFh *
* x2h 10000h through 17FFFh *
* x3h 18000h through 1FFFFh *
*********************************************************
*********************************************************
* Page Size = 64K Bytes (POS[0] or MARL = xxx10111b) *
* Page Reg WAC Memory Addresses Accessible by PC *
* ==================================================== *
* x0h 00000h through 0FFFFh *
* x3h 10000h through 1FFFFh *
*********************************************************
*********************************************************
* Page Size = 64K Bytes (POS[0] or MARL = xxx11xx1b) *
* Page Reg WAC Memory Addresses Accessible by PC *
* ==================================================== *
* don't care 00000h through 1FFFFh *
*********************************************************
(Page 12)
**************************************************
* ISA Memory Address Registers (MARL and MARH) *
**************************************************
The Memory Address Registers are used by the PC to program the size of the
memory window, and the location of the memory window in PC memory address
space. The window may be located anywhere in the 16M Byte address space of the
computer, but always begins on an even page boundary.
********************************************************
* Memory Address Register High (MARH) (Location 1Eh) *
********************************************************
This write-read register establishes the upper-most 8 bits of the 24-bit ISA
memory address (A23..A16). In conjunction with the LSB Memory Address
Register, the contents of this register establish the location of the WAC
memory window in the 16Megabyte memory address space of the computer:
***************************************************
* MARH Compared Against ISA *
* Bit Address Line (for Memory Access) *
* ==================================== *
* 7 A23 *
* 6 A22 *
* 5 A21 *
* 4 A20 *
* 3 A19 *
* 2 A18 *
* 1 A17 *
* 0 A16 (Program as 0 for 128K Mode)*
***************************************************
******************************************************
* Memory Address Register Low (MARL) (Location 1Fh) *
******************************************************
This write-read register establishes the low-order address bits for the WAC
memory window, and establishes the size of that window:
*****************************************************************************
* MARL Compared Against ISA *
* Bit Address Line (for Memory Access) *
* ============================================================== *
* 7 A15 (Program to 0 for 64k and 128k window modes) *
* 6 A14 (Program to 0 for 32k, 64k and 128k window modes) *
* 5 A13 (Program to 0 for 16k, 32k, 64k and 128k window modes)*
*****************************************************************************
(Page 13)
*****************************************************************************
* MARL Enable/Disable Bits *
* Bit FUNCTION *
* ================================================================ *
* 4 Enable (1) / Disable (0) PC access to WAC memory. *
* 0 Enable (1) / Disable (0) PC access to WAC memory. *
* (BOTH BITS MUST BE HIGH (1) TO ENABLE PC ACCESS TO WAC MEMORY) *
*****************************************************************************
*********************************************
* MARL Window Size Selector Bits *
* 3 2 1 Memory Window Size Selected *
* =================================== *
* 0 0 0 8K Bytes *
* 0 0 1 16K Bytes *
* 0 1 0 32K Bytes *
* 0 1 1 64K Bytes *
* 1 x x 128K Bytes *
*********************************************
*******************************************************
* ISA Adapter Identification (Locations 18h - 1Ch) *
*******************************************************
The ISA adapter features a 4-Byte read-only string located in its I/O
space. This is intended to serve as an aid to software for finding the
WAC in the PC I/O space. The card returns ASCII 'S','C','A','0' when read
at locations 18h, 19hh, 1Ah, and 1Bh (offset from start of I/O address block).
***********************************************************
* ISA Interrupt Identification/IUSC Reset (Location 1Dh) *
***********************************************************
The ISA adapter features a one-byte read-only location in the I/O space, which
allows software to read the setting of the DIP switch. Four positions (or
bits) are dedicated to the I/O address ranges and 3 positions (or bits) are
dedicated to the interrupt level. The interrupt level setting may affect system
performance. Conflicts with other system devices (ex. disk controller) should
be avoided. If further assistance is required to set these switches on the ISA
adapter, your local systems coordinator should be consulted.
*********************************************************
* IRQ ID ISA Interrupt DIP SWITCH *
* (Hex) Level Selected 1 2 3 *
* ========================================= * NOTE
* 0E0h IRQ9 ON ON ON * ----
* 0E1h IRQ5 OFF ON ON * May conflict with
* 0E2h IRQ4 ON OFF ON * disk controller
* 0E3h IRQ3 OFF OFF ON *
* 0E4h IRQ15 ON ON OFF *
* 0E5h IRQ14 (NOTE) OFF ON OFF *
* 0E6h IRQ11 ON OFF OFF *
* 0E7h IRQ10 OFF OFF OFF *
*********************************************************
Writing to this location causes a hardware reset to both of the Z16C32 IUSC
chips. (Write data is a don't care).
(Page 14)
***************************************
* Micro Channel POS Bit Assignments *
***************************************
POS bits are used to provide I/O address selection, Interrupt request
selection, and memory address (and window size) selection, and provide a
technique for identifying the adapter. These bits are accessed at setup time,
and reside at I/O addresses 0100h through 0107h in the computers I/O space.
***********************
* Adapter ID (0EFCDh) *
***********************
The WAC has been assigned an ID of 0EFCDh. This is read as two bytes, with
0CDh read from 0100h, and 0EFh read from 0101h.
********************************
* POS[0] - Memory Address LSB *
********************************
This register is similar to the ISA Memory Address Register - LSB, with the
following difference: Bit 0 is the Micro Channel "CDEN" bit, which
enables/disables operation of the entire adapter, not just the memory window
(as with the ISA adapter). Refer to the following tables:
*****************************************************************************
* POS[0] Compared Against Micro Channel *
* Bit Address Line (for Memory Access) *
* ============================================================== *
* 7 A15 (Program to 0 for 64k and 128k window modes) *
* 6 A14 (Program to 0 for 32k, 64k and 128k window modes) *
* 5 A13 (Program to 0 for 16k, 32k, 64k and 128k window modes)*
*****************************************************************************
*****************************************************************************
* POS[0] Enable/Disable Bits *
* Bit Name FUNCTION *
* ================================================================ *
* 4 MEMW Enable (1) / Disable (0) PC access to WAC memory. *
* 0 CDEN Enable (1) / Disable (0) PC access to WAC memory or I/O, and *
* Reset the Z16C32 IUSC chips (when LOW) *
*****************************************************************************
*********************************************
* POS[0] Window Size Selector Bits *
* 3 2 1 Memory Window Size Selected *
* =================================== *
* 0 0 0 8K Bytes *
* 0 0 1 16K Bytes *
* 0 1 0 32K Bytes *
* 0 1 1 64K Bytes *
* 1 x x 128K Bytes *
*********************************************
(Page 15)
************************************
* POS[1] - I/O Address Selector *
************************************
POS[1] performs the same function as positions 4-7 of the ISA adapter DIP
switch. Together with bit 3 of POS[3], the contents of POS[1] determine the
I/O address range used by the adapter, as follows:
***************************************************
* POS[1] Compared Against Micro Channel *
* Bit Address Line (for Memory Access) *
* ==================================== *
* 7 A15 *
* 6 A14 *
* 5 A13 *
* 4 A12 *
* 3 A11 *
* 2 (Not Used) *
* 1 (Not Used) *
* 0 (Not Used) *
***************************************************
*********************************
* POS[2] - Memory Address MSB *
*********************************
This register works in the same fashion as the Memory Address Register - MSB
on the ISA adapter. It establishes the upper-most byte of the 24-bit memory
address:
***************************************************
* POS[2] Compared Against Micro Channel *
* Bit Address Line (for Memory Access) *
* ==================================== *
* 7 A23 *
* 6 A22 *
* 5 A21 *
* 4 A20 *
* 3 A19 *
* 2 A18 *
* 1 A17 *
* 0 A16 (Not compared in 128K Mode) *
***************************************************
***************************************
* POS[3] - Interrupt Level Selector *
***************************************
POS[3] performs the same function as positions 1 through 3 of the ISA DIP
switch (sets the interrupt level). It also affects the I/O address range used
(Bit 3), and has three additional bits. Bit assignments for POS[3] are listed
in the two tables below:
(Page 16)
************************************************************************
* POS[3] *
* Bit NAME Function *
* ========================================= *
* 7 CHCK- (READ-ONLY). LOW (0) indicates that the WAC has *
* asserted the Micro Channel CHCK- (channel check) line, *
* as a result of a memory parity error. *
* 6 STAT- (READ-ONLY). LOW (0) indicates that the WAC has *
* status information in POS[4] and POS[5], corresponding *
* to the CHCK-. Not used on the WAC. *
* 5 SYNC (WRITE/READ). Controls timing of Micro Channel CHRDY *
* (wait/ready) signal. This bit must be programmed LOW *
* which specifies asynchronous CHRDY timing. *
* 4 (Not Used) *
* 3 IOA10 (WRITE/READ). Compared against Micro Channel address *
* line A10 for I/O access to the WAC. *
* 2 ILVL2 (WRITE/READ). Interrupt Level Selector Field *
* 1 ILVL2 (WRITE/READ). Interrupt Level Selector Field *
* 0 ILVL2 (WRITE/READ). Interrupt Level Selector Field *
************************************************************************
************************************************************************
* POS[3] Interrupt Level *
* 2 1 0 Selected *
* =================================== *
* 0 0 0 IRQ 9 *
* 0 0 1 IRQ 5 *
* 0 1 0 IRQ 4 *
* 0 1 1 IRQ 3 *
* 1 0 0 IRQ 15 *
* 1 0 1 IRQ 14 (May Conflict with Disk Controller) *
* 1 1 0 IRQ 11 *
* 1 1 1 IRQ 10 *
************************************************************************
(Page 17)
******************************************
* Programming Hints and Z16C32 Anomalies *
******************************************
1. The Zilog Z16C32 is used in its so-called "Non-Multiplexed" mode. This
implies that software must first point to a register before accessing that
register. Pointing is done by writing the register number to either the chips
DCAR (DMA Control/Address Register, for DMA) or CCAR (Channel
Control/Address Register, for COMM). After the register is accessed, the
"pointer" is automatically reset to point at the DCAR or CCAR.
2. The Z16C32 chip has a number of anomalies which are described in the Zilog
documentation package. One of these anomalies concerns the aforementioned
register pointer. Under certain conditions, the DMA portion of the Z16C32 will
reset the pointer data stored in DCAR. Thus is DMA is allowed to execute in
between the first I/O write (which does the pointing) and the following I/O
read or write (which does the data transfer), then the pointer may get reset,
which in turn means that the second transfer is to or from the DCAR, not the
intended register. The solution to this is to first disable the DMA, then do
the transfer, then re-enable the DMA, as follows:
(Reads the low-order 16 bits of receive DMA address, RARL)
mov dx,Zilog_A_DCAR ; Sets I/O address to DMA
mov ax,Disable_BRQ ; Disable the Z16C32 DMA request
out dx,ax ; This OUT disables DMA
; (Since this OUT went to DCAR, the
; pointer is still 0000 = DCAR).
mov ax,RARL ; Pointer to DMA receive address
out dx,ax ;
in ax,dx ; Read the RARL register (16 bits)
mov [LOW_ADDRESS],ax ; Save it away in memory...
; (Pointer is now back to DCAR)
mov ax,Enable_BRQ ;
out dx,ax ; Re-enable the DMA request.
3. In linked-list operation, the following method allows the programmer to
determine whether a given data frame has been transmitted.
Software can receive notification of completion of individual buffers by either
an "EOF/EOM" interrupt from the transmitter, or an "EOB" interrupt from the Tx
DMA. It can then tell which frame(s)/buffer(s) has been completely transmitted
by a two step process. Assuming that the ClearCount bit is initialized to 1, the
first step is to see whether the IUSC has zeroed the byte count in the linked list
entry for the buffer/frame. If so (indicating that the Tx DMA has started on the
buffer) software should then check the value of the Next Transmit Address
Register (NTAR). If the NTAR is outside the range of the address of the byte
count +2 to +6 inclusive, the Tx DMA channel is done with the buffer/frame.
(Page 18)
4. After the Z16C32 has been reset, its BCR (Bus Configuration Register) must
be programmed to configure certain hardware parameters. The bit fields for BCR
are to be programmed as follows (THIS MUST BE DONE FOR BOTH CHIPS):
BCR
Bit Value Name Function
=========================================
15 0 SepAd Separate Address (NO)
14 0
: : Reserved (all zeros)
6 0
5 0 IAckMode Interrupt Acknowledge Mode (Not Used
4 0 "
3 0 BRQTP Bus Request Totem Pole (NO)
2 1 16Bit Bus Size 16 Bits (YES)
1 1 /IRQTP Interrupt Request Not Totem Pole (YES)
0 0 SRightA Address Shift (NO)
Sample Code to perform this function is as follows:
(only after hardware reset of Z16C32 chips)
mov dx,Zilog_A_TDR ; point at transmit data register A
mov ax,06h ; BCR value
out dx,ax
mov dx,Zilog_B_TDR ; point at transmit data register B
mov ax,06h ; BCR value
out dx,ax
5. Initialization of the Z16C32 DMA function MUST configure certain bits of
the DMA Control Register (DCAR) in order for proper DMA operation, as follows:
DCR
Bit Value Name Function
=================================================
12 0 ALBVO Byte Ordering is Little-Endian
4 0 DCSDOut Don't drive D/C- and S/D- lines during DMA
3 1 1Wait Enable 1 Wait State for DMA memory access
2 0 UASAll Don't drive UAS and MS16 for every cycle
6. The Z16C32 for Link A is of a higher DMA priority than that for Link B.
The shared-memory arbiter passes its DMA grant to IUSCa, which then passes
control to IUSCb if IUSCa does not wish to transfer data. In all other
respects, the two channels are equivalent.
(Page 19)
******************************
* Crossover Cable Diagrams *
******************************
Figure 1. X.21 Crossover Cable Pin Diagram
Connector 1 Connector 2
1 <------------------------> 1
2 <------------------------> 4
3 <------------------------> 5
4 <------------------------> 2
5 <------------------------> 3
6 <------------------------> 7
7 <------------------------> 6
8 <------------------------> 8
9 <------------------------> 11
10 <------------------------> 12
11 <------------------------> 9
12 <------------------------> 10
13 <------------------------> 14
14 <------------------------> 13
15 15
Female Female
DB-15 DB-15
Figure 2. RX-232C/V.24 Crossover Cable Pin Diagram
Connector 1 Connector 2
1 1
2 <------------------------> 3
3 <------------------------> 2
4 <-|----------------------> 8
5 <-+
6 <------------------------> 20
7 <------------------------> 7
8 <----------------------|-> 4
+-> 5
9 9
10 10
11 11
12 12
13 13
14 14
15 <------------------------> 17
16 16
17 <------------------------> 15
18 18
19 19
20 <------------------------> 6
21 21
22 22
23 23
24 24
25 25
Female Female
DB-25 DB-25
(Page 20)
*********************************************************
* Hardware Shared Memory Specification Considerations *
*********************************************************
MC-A System Considerations
--------------------------
On MC-A Systems, the location of the 16KB Shared Memory is controlled
by the Reference Disk Installation procedure. Simply follow the
instructions for installing an Adapter in a MC-A system and the address
selected will work correctly.
ISA System Considerations
-------------------------
On ISA Systems, the location of the 16KB Shared Memory is selected by
the user. In determining this address, the user must select an address
above 0xC0000 that does not conflict with an already installed
adapter's shared memory and that starts on a 16KB boundary. However,
there is one additional performance consideration that must be
considered. Should the system that the WAC is being installed in have
less than 16MB of system memory, there is a way to configure the shared
memory such that data transfers take place with 16 bits at a time. Due
to an anomaly in ISA systems, if the address selected is at or above
1MB (0x100000), then data transferred into and out of this area will be
done with 16 bits at a time. Thus, if your ISA system has less than
16MB of memory, you should select an address at or above the top of
your installed system memory on a 16KB boundary. For example, if you
have 8MB of memory in your system, you could select 0x800000 as the
address for the 16KB shared memory window.
If your ISA system has 16MB or more of system memory, then you must
select an address between 0xC0000 and 0xFC000 on a 16KB boundary that
is not used by either another adapter or by system ROM. Consult your
adapter manuals and system manual to determine which addresses within
this range are not used and would thus be available for use by the WAC.
The negative aspect of using memory between 0xC0000-0xFC000 is that due
to the aforementioned ISA anomaly, data transfers into and out of this
area will only be 8 bits wide, not 16 bits. This approximately halves
the data transfer performance of the WAC adapter in an ISA system that
has 16MB or greater of system memory. Depending upon your WAC performance
goals, it may be desirable to remove 1MB of system memory so that you could
specify that vacated memory space above 1MB to contain the WAC 16KB shared
memory area. No performance measurements regarding this issue were made,
so you must make this determination based upon a careful review of the
system's use of memory.
(Page 21)
**********************************
* WAC Configuration Parameters *
**********************************
Parameter: WACCARDNUM
Value: Slot number (MC-A) [1..8] or Card Number (ISA) [0..15]
Description: Identifies the physical card associated with this logical
adapter number. For a Microchannel machine, this number identifies the
slot in which the card is located. For an ISA bus machine, this number
is the decimal representation of the setting of positions 7 - 4 of the
I/O Address DIP switch located on the upper edge of the card at the back
panel end (see ISA I/O Address Ranges Supported section).
----------
Parameter: WACPORTNUM
Value: Port number [0 - upper, 1 - lower]
Description: Identifies the physical port associated with this logical
adapter number. Port 0 is the upper port and Port 1 is the lower port.
----------
Parameter: RAMADDRESS
Value: 16KB Shared memory addr. [0C0000-FE0000]
Description: Specify the starting address for the 16KB shared memory on
the card. This address is required for ISA bus only, as it is setup
automatically in POS registers for the Microchannel card. The address
is only required on the definition of port 0 of each card. The address
must be on a 16KB (x'4000') boundary.
----------
Parameter: RTS
Value: Line Mode [ 0 - Constant RTS, 1 - Switched RTS ]
Description: Specifies whether half duplex transmission facilities or
full duplex transmission facilities are being used. The parameter
should be set to Switched RTS (Switched Request to Send (Line
Turnaround Required)) if either half duplex communications facilities
are being used, or the line is the secondary end of a multidrop SDLC
line. Most modern communications facilities are full duplex, and in
this case, Constant RTS should be specified for point-to-point lines
and for the primary end of SDLC lines.
(Page 22)
----------
Parameter: NRZI
Value: NRZI [ 0 - No, 1 - Yes ]
Description: Specifies the data encoding method for the communications
line. NRZI=YES uses an encoding that ensures that there is a signal
transition on the line at least every 6 bit times. This may be required
by some older modems to ensure stable clock recovery from the
data stream. NRZI must be specified identically at each end of the
communications line.
----------
Parameter: RS232MODE
Value: RS232/V.24 mode [0 -DTE, 1 -DTE_Pin24_TxC, 2 -DCE]
Description: Specifies clocking modes if the RS232/V.24 card is
installed. Specify 0 for DTE mode when connected to a modem that
generates the clocking. Specify 1 when connected to a modem that
requires the DTE to generate Tx clock on pin 24. Specify 2 to run in
DCE mode where the WAC provides both Rx and Tx clocks. DCE mode
requires the use of a crossover adapter described in the Technical
Reference Manual.
----------
Parameter: X21MODE
Value: RS422 mode [0] or X.21 Mode [1-4]
Description: Specifies clocking modes if the RS422/X.21 card is
installed. Specify 0 for RS422 DTE mode. (This requires the RS422
cable.) Specify 3 for normal X.21 DTE mode. Specify 4 for X.21 DTE
TxC_Echo mode (clock received on the S line is echoed on the B line to
eliminate Tx clocking skew on long cables). Options 1 and 2 are for
X.21 DCE mode and require a Crossover Connector as described in the
Technical Reference Manual. Specify 2 for normal X.21 DCE mode. Specify
1 for X.21 DCE TxC_Echo (the attached DTE must echo the clock back on
the B line to be used for clocking data into the Wide Area Connector).
(Page 23)
----------
Parameter: LINESPEED
Value: Line Speed in bits/second
Description: Specifies the clock speed to be used when the port
generates the clocking signal. When in normal DTE mode, the clocking is
generated by the modem or DSU/CSU, and this parameter is ignored. The
port generates clocking in all DCE modes, and in the RS232/V.24 Pin 24
mode (see the help panel for the RS232/V.24 Mode parameter). Note that
the clock speeds of 2M, 1.5M, 1M, 768K, 512K, 256K and 64K are actually
1.843M, 1.474M, 983.040K, 776.084K, 508.468K, 254.234K and 63.833K
precisely.
----------
Parameter: MAXDATA
Value: Maximum frame size to be sent and received
Description: Specifies the maximum size data frame that can be
processed, and is used by the MAC driver to allocate buffers. It must
be set larger than any expected data and headers size used by the
higher protocol, but should not be set unnecessarily high because of
the waste of buffer space. The default size allows RouteXpander/2 to
transmit LAN frames with a small header.
----------
Parameter: MACTYPE
Value: MAC Type Description
Description: Specifies the MAC Type that is visible to the higher layer
protocol drivers. These protocols may refuse to BIND to the MAC if MAC
Type does not conform to their requirements. The Wide Area Connector
saves this parameter, but does nothing with it.
----------
Parameter: MAXTRANSMITS
Value: Maximum number of outstanding transmit requests
Description: Allocates buffers for the specified number of transmit
requests. Transmit requests greater than this number must be retried by
the higher layers (but this is normally correct operation). If the
protocol window size is known, the number should be one greater than
it. If the number cannot be determined, the default is reasonable for
most situations.
----------
Parameter: MAXTXBUFS
Value: Maximum number of buffers per transmit request
Description: Used to allocate chaining space for separate buffers used
on a transmit request. For Communications Manager and TCP/IP, the
default is adequate.
(Page 24)
***********************************************
* Installation of More Than One WAC Adapter *
***********************************************
As mentioned before, for the ISA adapter, the I/O address ranges must be
different for each adapter in the system. Refer to the ISA I/O Address
Ranges Supported section for details.
As for the Microchannel adapter, since each WAC adapter uses a 16KB window
of memory, different I/O address ranges are automatically assigned for each
WAC adapter installed in the system. Therefore, no manual adjustment of
configuration parameters is required due to this design implementation.
