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- <!--
- Verilog - VHDL
- With help of:
- Loktev Nikola <loktev@niisi.msk.ru>
- -->
-
- <Define Name="VerString" Value="dStrings">
- <Define Name="VerComment" Value="dComments">
- <Define Name="VerWord" Value="dResWords">
- <Define Name="VerNumb" Value="dNumbers">
-
- <Scheme Name="Verilog">
- <!-- Numbers -->
- <RegExp Start="/\b(0x|X[\da-fA-F]+)\B/" Color0="VerNumb">
- <RegExp Start="/\b([0-9.]+(e|E[\-+]?\d+)?)\B/" Color0="VerNumb">
- <!-- Strings -->
- <RegExp Start='/("(.*?(\\\\)|[^\\])??")/' Color0="VerString">
- <RegExp Start="/('..??')/" Color0="VerString">
- <!-- Linear Comments -->
- <RegExp Start="/(\/\/.*$)/" Color0="VerComment">
- <Block Start="/\/\*/" End="/\*\//" Scheme="Comment" Color0="VerComment">
- <KeyWords MatchCase="True" Color="VerWord">
- <Word Name="tri1">
- <Word Name="tri0">
- <Word Name="wire">
- <Word Name="reg">
- <Word Name="assign">
- <Word Name="initial">
- <Word Name="fork">
- <Word Name="join">
- <Word Name="initial">
- <Word Name="parameter">
- <Word Name="always">
- <Word Name="integer">
- <Word Name="repeat">
- <Word Name="posedge">
- <Word Name="negedge">
- <Word Name="wait">
- <Word Name="input">
- <Word Name="output">
- <Word Name="table">
- <Word Name="endtable">
- <Word Name="primitive">
- <Word Name="endprimitive">
- <Word Name="inout">
- <Word Name="module">
- <Word Name="define">
- <Word Name="include">
- <Word Name="function">
- <Word Name="endfunction">
- <Word Name="task">
- <Word Name="if">
- <Word Name="then">
- <Word Name="else">
- <Word Name="endtask">
- <Word Name="$display">
- <Word Name="$fdisplay">
- <Word Name="$shm_probe">
- <Word Name="$fopen">
- <Word Name="$fclose">
- </KeyWords>
- </Scheme>
-