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1996-10-24
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Technical note for RISC OS 3.70 and StrongARM, 24-Oct-96
--------------------------------------------------------
You do not need to read this note in order to use the supplied patches;
read the ReadMe file instead. This note is for those who develop code
for RISC OS.
The SA110 (of revision less than 3, as specified in the ARM ID register)
has a bug in the User Register Store Multiple instruction (STM^). This is
the STM that is used to store user mode registers while in a privileged
mode. If the STM^ is executed while a data cache fill is completing the
store address for all but the first register may be wrong.
This should not affect any application or transient code (which will
execute in user mode), nor typical module code, but may affect a few
modules.
If you use STM^ in a module that is designed to work with StrongARM, we
recommend the following workaround for the problem:
Split the STM^ into a standard STM for the non banked registers
followed by an STM^ for the banked registers, adjusting the base
register afterwards as necessary.
A typical example follows:
;privileged mode
STMIA r0,{r1-r14}^
becomes:
;privileged mode
STMIA r0!,{r1-r12} ;store non-banked registers, writeback allowed
STMIA r0,{r13,r14}^ ;store banked registers
SUB r0,r0,#12*4 ;adjust base register back
The banked registers are R13 and R14 (it is extremely unlikely that FIQ
code would perform an STM^, since the extra banked registers are
precisely to avoid this need). It may be possible to optimise the base
register adjustment into the following code, depending on how the base
register is used subsequently.
Note that this sequence is non-atomic and does manipulate the base
register value. This is unlikely to be an issue, but the effect of an
interrupt (if enabled) during this sequence may need to be borne in mind.
Similar workarounds apply to other cases. However, you should note the
following standard ARM coding considerations:
- The first (non-^) STM cannot use writeback if the base register is in
the store list; this is unlikely, because it is not particularly
useful to store the base of the stored block in the block.
- The STM^ must not use writeback.
- If the base register is one of the banked registers, then a NOP
should precede the SUB instruction (since the SUB then uses a banked
register).