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KAYPRO
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KPNUROM.LBR
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KPORTS.ZQ0
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KPORTS.Z80
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Text File
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2000-06-30
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12KB
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424 lines
title KAYPRO 4-83 RESIDENT SOFTWARE PACKAGE
subttl SIO, PIO, and CTC equates
cseg
;
; ################################################################
; ## ##
; ## System device I/O routines for KBD, TTY and LST ##
; ## ##
; ################################################################
; ## LAST UPDATE: JULY 7,1982 [001] ##
; ## BY JIM NICKERSON ##
; ## CHANGED SIOA REGISTER 3 INIT TO AUTO ENABLE ##
; ## ADDED LIST STATUS FOR THE SERIAL PORT ##
; ## TTYOUT NOW THE SAME AS OUT WITH STATUS CHK ##
; ## CHANGE VECTOR PAD MAPPING ##
; ################################################################
; ## Fixed list status foulup. Moved thnsd here. 85/6/15 cbf ##
; ## Made bitport and bankbit available to external modules. ##
; ################################################################
;
entry kbdstat, kbdin, kbdout
entry ttystat, ttyin, ttyout, ttyostat
entry liststat, list, devinit
entry thnsd
entry bitport, bankbit
;
; ***************
; * sio equates *
; ***************
;
sio equ 04H; base address of sio
sioa0 equ sio+2; channel a command/status
sioa1 equ sio+0; channel a data
siob0 equ sio+3; channel b command/status
siob1 equ sio+1; channel b data
;
; write registers 0-7 and control bits
; init registers in the following order 0,2,4,3,5,1
;
wr0 equ 0; command register, crc reset, reg ptr
; bits 0-2 are register pointers to WRx and RRx
; bits 3-5 and commands as given bellow
null equ 0; null command
extrset equ 10H; reset ext/status interrupts
reset equ 18H; channel reset
ienrc equ 20H; Enable Int on Next Rx Character
rtip equ 21H; reset transmitter interrupt pending
errset equ 30H; error reset
retint equ 31H; return from interrupt
;
wr1 equ 1H; interrupt enable, Wait/Ready modes
esie equ 1H; external/status interrupt enable
tie equ 2H; transmitter interrupt enable
tid equ 0; transmitter interrupt disable
statav equ 4H; Status affects vector (z80 mode 2) (see WR2)
; bits 3-4 affect receive interrupt mode
rid equ 0; receive interrupts disabled
rifc equ 8H; receive interrupt on first char only
riep equ 10H; recv interrupts enabled, parity err,
; Special Recv Cond
rie equ 18H; same as riep but parity error
; not Special Recv Cond
;
wr2 equ 2; interrupt vect address/ptr (chan b only)
; interrupt address (z80 reg I+WR2=interrupt address)
; returned as is if not statav above in wr1
; if statav then bits 1-3 are modified as bellow:
; 000 ch b transmit buffer empty
; 001 ch b external/status change
; 010 ch b receive char available
; 011 ch b special receive condition
; (parity error, Rx overrun,
; framing error, end of frame(sdlc) )
; 1xx ch a (* same vectors as for channel b above *)
;
wr3 equ 3; receiver logic control and parameters
re equ 1; receiver enable
autoe equ 20H; auto enable
; (use dcd and cts to enable recv and xmt)
; bits 6-7 are receiver bits/character
rbits5 equ 0; 5 bits/character
rbits7 equ 40H; 7 bits/character
rbits6 equ 80H; 6 bits/character
rbits8 equ 0C0H; 8 bits/character
;
wr4 equ 4; control bits that affect both xmt and recv
pon equ 1; enable parity (parity on)
pstate equ 2; parity even not pstate = parity odd
; bits 2-3 are number of stop bits
syncmd equ 0; sync mode is to be selected
sbits1 equ 4; 1 stop bit
sbits5 equ 8H; 1.5 stop bits
sbits2 equ 0CH; 2 stop bits
; bits 6-7 control clock rate
cr1 equ 0; data rate x1=clock rate
cr16 equ 40H; x16
cr32 equ 80H; x32
cr64 equ 0CH; x64
;
wr5 equ 5; control bits that affect xmt
te equ 8H; transmit enable
break equ 10H; send break
; bits 5-6 are number of bits/character to transmit
tbits5 equ 0; 5 or less bits/character
tbits7 equ 20H; 7 bits/character
tbits6 equ 40H; 6 bits/character
tbits8 equ 60H; 8 bits/character
rts equ 2; RTS output
dtr equ 80H; DTR output
;
wr6 equ 6; sdlc transmit sync character
wr7 equ 7; sdlc receive sync character
;
; read registers 0-2 and status bits
rr0 equ 0; general recv and xmt status
rca equ 1; receive character available
intped equ 2; interrupt pending (ch a only)
tbe equ 4; transmit buffer empty
synhnt equ 10H; sync/hunt
dcd equ 8H; DCD input
cts equ 20H; CTS input
xmtundr equ 40H; transmit underrun/ EOM
brk equ 80H; break/abort status
;
rr1 equ 1; Special Rcv conditions and Residue codes
; bits 4-7 are special receive conditions
rpe equ 10H; parity error
rovr equ 20H; Rx overrun error
framerr equ 40H; framing error
;
rr2 equ 2; interrupt vector address/pointer
;
; ***************
; * pio equates *
; ***************
;
pio equ 08H; base address of pio
pioac equ pio+1; pio a control
pioad equ pio+0; pio a data
piobc equ pio+3; pio b control
piobd equ pio+2; pio b data
;
spio equ 01CH; base addr. of pio (system status bits port)
spioac equ spio+1; pio a control
spioad equ spio+0; pio a data
spiobc equ spio+3; pio b control
spiobd equ spio+2; pio b data
;
bitport equ spioad; system bit port for status and control
bankbit equ 080h; switch to ROM bank
; 0 drive sel A:
; 1 drive sel B:
; 2 n/c
; 3 centronics i/o ready line
; 4 centronics i/o data strobe
; 5 single density (not 5 is double density)
; 6 drive motor off (not 6 is motor on)
; 7 rom enable (not 7 is rom off)
;
; control register
setiv equ 0; set interrupt vector, bits 1-7 are vect addr
;
som equ 0FH; set operating mode. bits 6-7 specify mode
mode0 equ 0; output
mode1 equ 40H; input
mode2 equ 80H; bidirectional
mode3 equ 0C0H; control (bit by bit i/o,
; mode3 command is followed by
; byte where bit pattern specifies i/o bits
; 1=input, 0=output
;
sicw equ 7H; set int control wd, bits 4-7 are params
imask equ 10H; bit mask follows )
hghlow equ 20H; high/low ) mode 3 only
andor equ 40H; and/or of bits to gen interrupt )
intena equ 80H; enable interrupt (bit low disable ints)
;
intcmd equ 03H; set interrupt enable/disable
; without changing status as sicw
;
; ***************
; * ctc equates *
; ***************
;
ctc equ 18H; ctc base address
ctc0 equ ctc+0; ctc channel 0
ctc1 equ ctc+1; ctc channel 1
ctc2 equ ctc+2; ctc channel 2
ctc3 equ ctc+3; ctc channel 3
;
; channel control register bits
ctccmd equ 01H; ctc command byte
ctcint equ 80H; interrupt enable
ctcm1 equ 40H; set ctc mode is counter
ctcm0 equ 00H; set ctc mode is timer
range equ 20H; timer prescaler factor is 256
; (not range is 16)
slope equ 10H; edge triger positive
; (not slope is negative edge)
trigger equ 8H; ext trigger
ltc equ 4H; load time constant
; (followed by time constant)
rsetctc equ 2H; reset channel
;
ctcivec equ 0; set ctc interrupt vector,
; bits 3-7 are vector addr
ctcvmsk equ 0F8H; interrupt vector mask to strip bits 0-2
;
; ***************
; * baud rate *
; ***************
;
bauda equ 00H; baud rate generator for serial chan a
baudb equ 0CH; baud rate generator for serial chan b
;
; baud rate factors, output to baudx to select baud rate
baud10 equ 02H; 110 baud rate
baud30 equ 05H; 300 baud rate
baud12 equ 07H; 1200 baud rate
baud24 equ 0AH; 2400 baud rate
baud48 equ 0CH; 4800 baud rate
baud96 equ 0EH; 9600 baud rate
baud19k equ 0FH; 19.2k baud rate
;
subttl I/O configuration tables
;
iotabint: ; i/o device initialization table
; first byte is port #
; second byte is byte to send to port
db (iotblend-iotabint)/2 ; table length in arguments
;
; init sio channel b
db siob0, reset; reset sio channel
db baudb, baud30; 300 baud
db siob0, wr4
db siob0, sbits1 or cr16; one stop bit, 16x clock
db siob0, wr3
db siob0, re or rbits8; recv enable, 8 bits/char
db siob0, wr5
db siob0, te or tbits8 or dtr; xmt enbl, 8 bits, dtr on
db siob0, wr1
db siob0, tid or rid; xmt & recv interrupts disabled
;
; init sio channel a
db sioa0, reset; reset sio channel
db bauda, baud30; 300 baud
db sioa0, wr4
db sioa0, sbits1 or cr16; one stop bit, 16x clock
db sioa0, wr3
db sioa0, re or rbits8 or autoe; rcv enbl, 8 bits, auto enbl
db sioa0, wr5
db sioa0, te or tbits8 or dtr; xmt enbl, 8 bits, dtr on
db sioa0, wr1
db sioa0, tid or rid; xmt & recv interrupts disabled
;
; init pio used form system control bits
db spioac, intcmd; disable interrupts
db spioad, 10000001B; set system status bits
; (before setting mode!)
db spioac, som or mode3; set mode to #3
db spioac, 00001000B; bit pattern for mode 3
;
; init pio used to drive printer
db pioac, intcmd; disable interrupts
db pioac, som or mode0; set mode to #0 (output)
db piobc, intcmd; disable interrupts
db piobc, som or mode1; set mode to #1 (input)
iotblend: ; end of table
;
; Initialize i/o devices
devinit:
ld hl,iotabint
ld b,(hl); number of bytes to send to i/o devs
iolp: inc hl
ld c,(hl); port to send
inc hl
ld a,(hl); byte to send
out (c),a
djnz iolp
; " "
; Check the CPU clock speed against a 300 baud SIO port.
; Depends on the ZILOG SIO characteristics.
; a,f,b,c,h,l
chkspd: ld hl,0
ld b,10
chks1: xor a
out (siob1),a; jam the output buffer
out (siob1),a; with nulls
out (siob1),a
out (siob1),a
chks2: inc hl
in a,(siob0); and see how long till free
and tbe
jp z,chks2; not free yet
djnz chks1; do again, summing to average.
ld c,h; hl = 5f00 approx at 2.5 mhz
xor a
ld b,a
add hl,hl; Scale to get count
adc a,a; for a 10 millisec pause.
add hl,hl
adc a,a
add hl,hl
adc a,a
ld l,h
ld h,a
add hl,bc
ld (clkspd),hl
ret
;
subttl Device I/O handlers
;
kbdstat:
in a,(siob0); kbd char avail?
and rca
ret z; 0=no char
ld a,0FFH; FF=char avail
ret
;
kbdin: call kbdstat; loop till char avail
jr z,kbdin
in a,(siob1); get char
call kbdmap; map out funny vector pad chars/nums
ret
;
kbdout: in a,(siob0); xmit buffer empty?
and tbe
jr z,kbdout
ld a,c; out character
out (siob1),a
ret
;
kbdmap: ld hl,mapin; input map table
ld bc,mapout-mapin; table length
cpir; search table
ret nz; not found
ld de,mapin; make hl=table index
or a; hl-mapin=index
sbc hl,de
ld de,mapout-1; index
add hl,de
ld a,(hl); get char from mapout
ret
;
mapin: db 0F1H, 0F2H, 0F3H, 0F4H; up, down, left, right arrows
db 0B1H, 0C0H, 0C1H, 0C2H; 0,1,2,3
db 0D0H, 0D1H, 0D2H, 0E1H; 4,5,6,7
db 0E2H, 0E3H, 0E4H, 0D3H; 8,9, '-', ','
db 0C3H, 0B2H; return, '.'
db 0FFH; end of mapin table
mapout: db 80H, 81H, 82H, 83H; vector pad, xlate in bios
db 84H, 85H, 86H, 87H
db 88H, 89H, 8AH, 8BH
db 8CH, 8DH, 8EH, 8FH
db 90H, 91H
;
ttystat:
in a,(sioa0); serial port status input
and rca
jr comout
;
ttyin: call ttystat; is a char ready?
jr z,ttyin
in a,(sioa1)
ret
;
ttyout: in a,(sioa0); output a char to serial port
and tbe
jr z,ttyout; xmit buffer full?
ld a,c
out (sioa1),a; xmit character
ret
;
; test status of serial output
ttyostat:
in a,(sioa0)
and tbe; TX BUF FULL ?
jr comout
;
; list port centronics equates
pready equ 08h; bit in bit port
pstrob equ 10h; bit in bit port
;
; Centronicts printer port status
liststat:
in a,(bitport)
and pready
; " "
; common status output
comout: ret z; 0=busy
ld a,0FFH; FF=ready
ret
;
list: call liststat; is printer busy?
jr z,list
ld a,c
out (pioad),a; output char to printer
in a,(bitport); strb. printer
or pstrob
out (bitport),a
and not pstrob
out (bitport),a
ret
;
; Delay for (b) units of 10 millisec.
; a,f,b
thnsd: push hl
td1: ld hl,(clkspd); approx 1670 at 5 mhz
td2: dec hl
ld a,h
or l
jp nz,td2
djnz td1
pop hl
ret
;
;
dseg
entry clkspd; for boot pre-initialization
;
clkspd: ds 2; holds the CPU clock rate for timer
;
end