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EXAMPLES
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1993-01-07
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(c) Copyright 1992 Genashor Corp. All Rights Reserved.
The following summary should help you understand the accompanying
network description (.net) files. The SIMIC User's Guide contains
a complete description of SIMIC's Network Description Language (SNL).
This file also contains descriptions of all SIMIC primitives used in
these demonstration circuits.
Structure Of Circuit Descriptions
---------------------------------
Network topology is specified in the !LOGICAL section of the network
description file. SIMIC supports a general hierarchical network
description capability, where the top-level circuit (the "main
type") and constituent subcircuits (macros) consist of:
(a) a TYPE statement, which specifies the macro's input,
output, and bidirectional (bus) ports and, optionally,
their electrical characteristics, followed by
(b) one or more PART statements, which specify the macro's
internal elements and their interconnections. The internal
elements can either be SIMIC primitives or instances of
other macros.
Normally, each statement is logically terminated by a carriage-
return (or newline). Long statements that require more than one
line may be continued by placing a dollar sign ($) at the end of
each line to be continued.
Comments may be added inside of, and between, macro definitions; they
follow the "COMMENT=" or "C=" keyword.
TYPE And PART Statements Contain Keyword-Fields
-----------------------------------------------
Each TYPE and PART statement contains keyword-fields separated by
whitespace - either spaces or tabs. For example, the TYPE statement
in demonstration file bushold.net is:
Type=bushold I=EnA,DataA,EnB,DataB O=E Olod=1
This statement begins the definition of the circuit. The first
keyword field, "Type=bushold" specifies the circuit type (or name)
as "bushold". The second keyword-field, "I=EnA,DataA,EnB,DataB",
specifies this macro's four input pins; "EnA", "DataA", "EnB", and
"DataB". The third keyword-field, "O=E", specifies this macro's
single output pin, named "E". The last keyword-field, "Olod=1",
specifies that the load associated with output pin E is 1.
Each PART statement following the TYPE statement describes a component
in the macro. The PART statement assigns the component a unique
instance name within the macro, specifies the component's type (either
a SIMIC primitive or the name of another macro), and names the signals
connected to the component's input, output, and bidirectional (bus)
pins. The PART statement may optionally specify component electrical
characteristics such as output delays, pin loading, and output drive.
For example, the first component of the bushold circuit can be
specified as:
Part=u1 Type=tpadn I=EnA,DataA O=Bus Odel=Del10
The first keyword-field, "Part=u1", assigns the name "u1" to this
component. The second keyword-field, "Type=tpadn", specifies that
this component is a tpadn, a SIMIC primitive. The third keyword-field,
"I=EnA,DataA", specifies the two input signals (which are also
connected to the identically-named macro pins). The third keyword-
field, "O=Bus", specifies that the internal signal named "Bus" is
connected to this component's output. Finally, the keyword-field
"Odel=Del10" specifies that the global delay table named "Del10"
describes the delay characteristics of this output.
!FORMAT Statements Eliminate Entry Of Most Keywords
---------------------------------------------------
Since most PART statements will, with minor exception, contain the
same keywords, it should not be necessary to enter these common keywords
in every PART statement. The !FORMAT statement informs SIMIC of the
keyword-field order in all PART statements that follow it. Keywords
need only be entered for those PART statements that deviate from the
!FORMAT specification.
For example, the statement:
!FORMAT Part= Type= I= O= Odel=
inform SIMIC that all keyword-fields should be expected to occur in
the specified order (first the "Part=" keyword-field, then the
"Type=" keyword-field, etc.). If a subsequent PART statement exactly
utilizes these keyword-fields in this specified order, only the right-
sides of the keyword-fields need be specified. Otherwise, complete
keyword-fields should be specified. Thus, having described this format,
the first component of the bushold circuit can be instantiated with:
u1 tpadn EnA,DataA Bus Del10
which is equivalent to:
Part=u1 Type=tpadn I=EnA,DataA O=Bus Odel=Del10
PART statements containing keyword-fields other than those specified
in the !FORMAT statement can be handled most conveniently by first
specifying these keyword-fields last. For example, the last component
instantiation in the bushold circuit
u5 and Bus E Del10 Ilod=1
adds the keyword-field "Ilod=1", and is equivalent to the statement
Part=u5 Type=and I=Bus O=E Odel=Del10 Ilod=1
Keywords Used In Demonstration Network Description Files
--------------------------------------------------------
B specifies bidirectionals
BLOD specifies loading at bidirectionals (default is zero)
I specifies inputs
ILOD specifies loadint at inputs (default is zero)
O specifies outputs
OCHANGE specifies the value of (identical) rise and fall delays
(constant or load-dependent - default is zero)
ODEL specifies delay by referencing global delay table names
ODRIVE specifies output drive (POWER-RAIL, DRIVING, RESISTIVE,
or FLOATING -- default is DRIVING)
OFALL specifies fall delay (constant or load-dependent
- default is zero)
OLOD specifies loading at outputs (default is zero)
ORISE specifies rise delay (constant or load-dependent
- default is zero)
PART specifies component instance name
TIMING-CHECKS specifies flip-flop timing checks
TYPE specifies macro name in TYPE statements, instance type
in PART statements
SIMIC Primitives Used In Demonstration Network Description Files
----------------------------------------------------------------
AND AND gate (1 <= number of inputs <= 32767)
BTGN ideal (resistanceless) switch having two bidirectional pins
and one control input; switch is ON (bidirectional
pins are connected) when the control input is logic-1,
and OFF when the control input is logic-0.
DPCF positive-edge-triggered D-flip-flop with active-low RESET and
SET asynchronous inputs. input ordering is NR,NS,CL,D.
output ordering is Q,NQ (the NQ output is optional)
INV inverter
NAND NAND gate (1 <= number of inputs <= 32767)
NOR NOR gate (1 <= number of inputs <= 32767)
TNCF negative-edge-triggered T-flip-flop with active-low RESET and
SET asynchronous inputs. input ordering is NR,NS,CL.
output ordering is Q,NQ (the NQ output is optional)
TPADN tristating driver with two inputs and one outut. input ordering
is EN,D. when EN is logic-1, the output is assigned the
value of the D input. when EN is logic-0, the output
tristates.
Reserved Signal Names
---------------------
Two signal names are reserved for special signals:
ONE - logic-1
ZERO - logic-0