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(c) Copyright 1992 Genashor Corp. All Rights Reserved.
This file describes the SIMIC demonstration files. Some additional
information can be obtained by reading the "SIMIC Engineering Guide
for IC Design Verification" by Genashor Corp.
Only a small percentage of SIMIC features are described in these
demonstrations. The "SIMIC User's Guide" by Genashor Corp describes
SIMIC's range of capabilities.
Each Demonstration consists of a network description, in a file with
extension .net. Most Demonstrations also have a second file, with
extension .run, which contains a number of SIMIC commands to
automatically perform the simulation. Each .run file contains
commentary to explain each step.
A simulation is run by issuing the command:
simic <command_file>
where <command_file> is the name of the "run" file for that
demonstration. For example, if a demonstration consisting of two
files: example1.net and example1.run, exercise this demonstration
with the command:
simic example1
Alternatively, the same operation can be accomplished by entering the
command:
simic
SIMIC will issue its prompt, ">>:", requesting interactive input. In
response to this prompt, simply type the command:
execute file=example1
SIMIC, by default, is case insensitive. The demonstration files use
mixed case only to improve readability. It is a good idea to make a
hardcopy of each file for viewing while running the demonstrations.
Network Description Overview:
a) Global Delay Table. Delay characteristics are specified
in the !Delay section of the file. Each delay relation
is assigned a unique name, allowing multiple element
instances to share delay characteristics through symbolic
references. Delay tables can be designed for different
operating conditions, and a specific table can chosen for
circuit compilation. Typical tables might include pre-
and post- radiation hardening characteristics, or the
effects of different supply voltages. Delays can be
specified as absolute values, or delay vs. loading curves.
Delay vs. loading curves may be specified in intercept/slope
format or two point format (delays at two different loading
conditions). SIMIC adds all loading on each signal (wiring
capacitance and capacitance at all driven load pins), and
extrapolates the delay for this total loading from the
referenced delay curve. For any element, MINIMUM, TYPICAL
and MAXIMUM values may be specified, and then chosen
and/or scaled interactively.
b) Annotation. These include !Documentation section(s), which
allow clean addition of large amounts of text, and Comments,
beginning with the Comment keyword (C=), for single line
commentary. In addition, Remarks (R=) allow information to
be conveyed to the user during circuit compilation (for
example, to warn the user about constraints on using a given
macro (TYPE)).
c) Electrical Characteristics. Specifications such as drive
strength (ODrive) and loading (Ilod). These and other
characteristics can be viewed in the listing (.lst) file
created by the circuit compiler.
d) Network Topology. The circuit's netlist is specified in the
!Logical section of the file. SIMIC supports a general
hierarchical network description language in which each
macro (subcircuit) is defined by a TYPE statement, which
specifies the macro's input, output, and bidirectional (bus)
ports (and optionally, their electrical characteristics),
followed by PART statements, which specify the macro's
internal elements and their interconnections. The internal
elements can either be SIMIC primitives or instances of
other macros.
See the file snl.txt for descriptions of the topological constructs
and the SIMIC primitives used in the demonstration testcases.
Testcase #1 - The Bus Hold Circuit. (bushold.net and bushold.run)
Run Command Description:
a) Define File=bushold
This command specifies that all files will have the default
name "bushold". Contents of files are distinguished by the
extension attached to this name. For example, in this
demonstration, SIMIC will generate a "listing" file of the
compiled circuit, as no name for this file was specified,
the information will be placed in a file named "bushold.lst".
b) Get Type=bushold Report=all
The "Get" command is used to compile/retrieve circuit
descriptions, timing, and loading information.
"Type=bushold" specifies that SIMIC should compile the
circuit named "bushold". "Report=all" specifies that a
"listing" file should be generated and all information
should be included. This listing file will contain a
description of the flattened circuit and the electrical
characteristics of each element.
c) Define Wall.4 = 1000 @200 0000 @210 0011 @260 0001
Apply Patterns=Wall
Creates and applies input stimulus to the circuit.
SIMIC has a very flexible input stimulus language. It
allows hierarchical patterns to be described, containing
loops, absolute and relative positioning of patterns,
stimulus grouping, etc. "Define Wall.4" specifies the
creation of a 4-bit wide pattern sequence named Wall. The
"W" in Wall specifies that the patterns are temporal (Each
pattern is positioned in time). This form is the most
frequently used by other simulators, but is only one of
three forms (and typically the least used) in SIMIC. In
this command, four input states (1000, 0000, 0011, and
0001) are described and applied at times (0, 200, 210, and
260) respectively. "Apply Patterns=Wall" attaches this
sequence to the primary inputs (EnA, DataA, EnB, DataB)
respectively (The order defined in the network description).
d) Print List=EnA,DataA,EnB,DataB*Bus*E Change:
No Print Pstep:
Specifies what, when and how to output signal information
during simulation. The "Print" command is used to output
information to the terminal (stdout). The "Write" command
is identical to "Print", except this command sends the
output to a file, with default extension ".wrt". Write
and Print commands operate independently, and may coexist
in the same simulation run.
"List=" indicates that a list of signals to output will
follow. The asterisks (*) specify that a blank vertical
column should be inserted in order to make the output more
readable. "Change:" indicates that SIMIC should output
whenever any one of the signals on the list changes state.
"No Print Pstep:" specifies that SIMIC should NOT output
each time the circuit stabilizes (all internal activity
ceases -- this is the default condition causing Print and
Write output).
SIMIC uses a single-character representation for each of the
15 possible combinations of signal strength and value.
You may force SIMIC to display a four character
representation (0, 1, X, and Z), suppressing strength
information by adding the command:
Print Values=Levels
prior to the simulate command.
e) No Warn Unstable:
SIMIC will, by default, issue a warning message if the
circuit leaves fundamental mode of operation (the circuit
is still responding to an input change when a new input
change occurs). Since loss of fundamental mode of operation
is not a problem for this circuit, the warning message is
not meaningful here.
f) Simulate
This tells SIMIC to perform the simulation.
g) Quit
This ends the SIMIC session.
Testcase #2 - Paralleled Devices. (parallel.net)
This demonstrates SIMIC's ability to merge electrical characteristics
of simple combinatorial gates and switches. In this circuit two
buffers are placed in parallel. This demonstration will also walk
you through a totally interactive session in SIMIC.
a) Enter SIMIC.
Do this with the command:
simic
at your system's prompt. The SIMIC session should begin
and SIMIC should issue the prompt:
>>:
indicating that SIMIC is requesting command input.
b) Specify a default file name. File names for SIMIC input
or output are then derived from this name, by default.
If not specified, the default name is "noname". In this
example, use the name "parallel":
define file=parallel
If you mistyped this command, just reenter it with the
correct value to replace the mistyped one.
c) Compile the circuit description. We also would like a
file containing the flattened circuit description and its
simulation properties. This is done with the command:
get type=parallel report=all
We could quit this session and look at the listing file,
parallel.lst, to see the resulting information. We can
also interrogate the circuit properties of interest
interactively. Examples are:
?delay list:
which will display the rise and fall values for all signals
and:
?loading list:
which will display the loading information for all signals.
You will note that the AND gate generating signal C has
larger delays than the equivalent ANDs that are paralleled
and generates signal B.
d) Leave SIMIC session with the command:
quit
Testcase #3 - Dynamic Loading. (dynamic.net and dynamic.run)
This demonstrates SIMIC's ability to adjust element delays (even those
undergoing a state transition) based on the current and dynamic loading
conditions provided by ideal switch elements.
Run Command Descriptions:
a) Define File=dynamic
Specifies the default file name, as in the previous examples.
b) Get Type=dynamic
Requests SIMIC to compile the circuit description.
c) Define pin.1= do 2 (0 1)
Define pen.1.2= 0 1
Apply Pattern=pin List=in
Apply Pattern=pen List=b
Defines and applies stimulus values. In this case the
stimuli are defined as simulate-until-stable patterns.
Each pattern is applied only when the circuit has finished
responding to the previous stimulus. This method of
stimulus application:
1) Prevents leaving fundamental mode of operation,
2) allows identification of slow paths easily, and
3) makes available a number of sophisticated
troubleshooting techniques uniquely found in SIMIC.
"Define pin.1= do 2 (0 1)" defines a pattern sequence
called "pin" that will be applied to one signal. In this
pattern the sequence (0 1) will be applied twice.
"Define pen.1.2= 0 1" defines a pattern sequence called
"pen" that will be applied to one signal and whose default
duration for each vector is two patterns. The sequence
(0 1) will be applied. Note that the default duration
specifies that the sequence will really be (0 0 1 1).
"Apply Pattern=pin List=in" attaches the sequence "pin"
to signal "in", and "Apply Pattern=pen List=b" attaches
the sequence "pen" to signal "b".
d) Print List=in*b*a*out Change:
Describes which signals to output, and when output should
occur. In this case, We wish to display the values of the
signals in, b, a, out. Again, the asterisk (*) indicates
that a blank vertical column is requested for readability,
and "Change:" indicates that we want output whenever any
signal on the list changes.
e) Simulate
Initiates simulation.
f) Quit
Ends the SIMIC session.
Testcases #4 and #6 combined - Conflicts and Conflict resolution.
This demonstrates SIMIC's ability to detect, and, if possible,
resolve conflicts on wire-ties.
Run command description:
a) Define File=conflict
Defines the default file name.
b) Get Type=Conflict
Compiles the circuit called "Conflict".
c) Define Pa.2= 10 X1
Define Pb.2= 11
Apply Pattern=Pa List=EnA,DataA
Apply Pattern=Pb List=EnB,DataB
Defines and applies the stimulus to the input signals.
As before, the stimulus mode is simulate-until-stable
patterns. In pattern #1 part A is driving a logic-0,
while part B is driving a logic-1, a "real" conflict
situation. During simulation, notice the explicit
conflict message, indicating the condition, and the
signals that are in conflict. In Pattern #2 part A
is either driving a logic-1 or is tristating, due to the
unknown logic value on its enable. Since part B is still
driving a logic-1, the "conflict" can be resolved as a
logic-1.
d) Print List=EnA,DataA*EnB,DataB*Bus*C
Outputs the specified signals whenever the circuit becomes
stable.
e) Simulate
Initiate simulation.
f) Quit
End SIMIC session.
Testcase #5 - Oscillations. (oscil.net and oscil.run)
This demonstrates SIMIC's ability to trap an oscillation (Excess
activity on a signal for a given circuit input state), and squelch
it (by turning it into an X). This easily uncovers Meta-stable
states in the circuit.
Run Command Descriptions:
a) Define file=oscil
Defines a default filename.
b) Get Type=oscil
Compiles the circuit named oscil
c) Define Pab.2= 00 11
Apply Pattern=Pab
Defines a pattern sequence and applies it to the input
signals. Again, we are using simulate-until-stable format.
d) Print List=a,b*q,nq Change:
Specifies to output the listed signals whenever their values
change.
e) Simulate
Do the simulation.
f) Quit
Leave SIMIC.
Testcase #7 Timing Verification - (ftv.net and ftv.run)
This testcase demonstrates SIMIC's unique capability to detect timing
violations functionally.
Network Description Highlights:
a) Timing hazard information. Information describing timing
checks may be added to all SIMIC flip-flops and D-Latch
primitives. These are contained within a timing-check
block (Timing-checks= begin; ... end;) Each timing check
may be described as an constant value, or as a load-
dependent value. In addition, you can control whether a
timing violation message is issued, or whether the flip-flop
state should be set to unknown (X), on a per instance/
per timing-check basis. In this example, the pulse-width
limit on the negative reset input is set at 20.
Run Command Description:
a) Define File=ftv
Defines the default file name.
b) Get Type=ftv
Compile the circuit called ftv.
c) ?Checks Part=q
Have SIMIC list the timing-check limits and options set
for part Q.
d) Define Pat.3=000 011
Apply Pattern=Pat
Define Period=1000
Define Tclock.RZ=250,750
Define Treset.RO=500,510
Define Tdata.NRZ=0
Apply Timing=Tclock List=c
Apply Timing=Treset List=nr
Apply Timing=Tdata List=d
You should be familiar with the first two commands from
previous examples. It seems exactly like the simulate-
until-stable format discussed previously. However, in
this example, we will demonstrate the third method for
describing stimulus, Timing Generators. This method
emulates modern Automatic Test Equipment (ATE). Testers
require that a master clock period be define, and timing-
generators be assigned to inputs to produce waveforms
relative to a master clock period. In our example,
we describe the period with the "Define Period" command,
and each timing generator with the "Define T..." command.
Define Period=1000
Sets the master period to 1000 time-units.
Define Tclock.RZ=250,750
Defines a RZ (Return to Zero) timing generator. If the
pattern is a 0, the waveform remains at a logic-0.
If the pattern is a 1, then the waveform goes high at
time 250 and then low again at time 750 (relative to the
start of the period).
Define Treset.RO=500,510
Defines a RO (Return to One) timing generator. If the
pattern is a 1, the waveform remains at a logic-1. If
the pattern is a 0, then the waveform goes low at time
500 and then high again at time 510 (relative to the
start of the period).
Define Tdata.NRZ=0
This defines an NRZ (Non-Return to Zero) timing
generator. The waveform obtains the pattern's value at
time 0 (relative to the start of the period). If no
timing generator is specified for an input, this is SIMIC's
default.
SIMIC also allows description of Drive Envelopes (when an
input changes from drive to tristate and tristate to drive),
supports time-set switching (changing timing generators
on an input during simulation), and strobe definitions
(when to sense for an output or in/out value).
In this demonstration, we could have used SIMIC's waveform
description to accomplish the same task. The equivalent
waveform description for the timing generator waveforms
would be:
Define Wdata.1.1000= 0 1
Define Wreset.1= 1 &500 do 2 (0 &10 1 &1000)
Define Wclock.1.500= 0 &250 do 2 (1 0)
Apply Pattern=Wdata List=d
Apply Pattern=Wreset List=nr
Apply Pattern=Wclock List=c
Where the & indicates that the following integer represents
the duration for the previous pattern. For example the
definition for Wreset reads:
"Apply a logic-1 at time 0 and hold it for 500 time-units,
followed by the repetition of the following sequence twice:
Apply a logic-0 and hold it for 10 time-units followed by
a logic-1 held for 1000 time-units."
e) Print List=nr,d,c*q Change:
No Print Pstep:
Specifying to print the listed signals when any one of them
change, and do not output each time the circuit becomes
stable.
f) Simulate
Simulate the circuit.
g) Restore Tnum=0
This command returns the circuit to an uninitialized
(pre-simulation state). We are doing this in order to
show what would happen if there were no functional
timing checks.
h) No Warn Part=q Pw:
Turn off the warnings for any pulse-width violation on
part Q.
i) No Xpropagate Part=q Pw:
Suppress setting the flip flop for a functional violation
on part Q.
j) Simulate
Simulate the circuit (again).
k) Quit
Leave the SIMIC session.
Testcase #8 - Interactive Debugging (div7.net and div7.run).
In this demonstration we provide an interactive debugging session
encapsulated in a run file. This provides a demonstration of how
easily SIMIC can isolate problems in the circuit.
Run Command Descriptions:
a) Define File=div7
Define the default name for files.
b) Get type=divide_by_7
Compile the circuit.
c) Define Preset.1= 0 1
Define Pclock.1= 0 do 8 (1 0)
Apply Pattern=Preset List=reset
Apply Pattern=Pclock List=clock
Define and apply the stimulus. We used simulate-until-
stable patterns here.
d) Define Vq.Posint=q4,q2,q1
Group scalar signals q4, q2, and q1 into an array called
"Vq". When displaying this array, it will be done as a
positive integer (Posint). Arrays can also be explicitly
defined in the network description. SIMIC recognizes
arrays in all commands and acts on them collectively.
Other display formats include (binary, octal, hexadecimal,
1's complement, and 2's complement).
e) Print List=clock,reset*q4,q2,q1*Vq
Specify the simulation output. Note here the use of our
defined array, Vq.
f) No Xpropagate Spike:
This option prohibits detected spikes from propagating as
a pulse of unknown value. In effect, all spikes will be
filtered from the simulation. This will demonstrate how
most other simulators would handle this circuit.
g) Simulate
Initiate simulation. The things to notice in the simulation
results are:
1) Our defined array, Vq. The header indicates this
signal as *Q to indicate that this signal does not
exist in the network description.
2) The simulation results. In this simulation, the
circuit appears to be operating properly.
3) The message:
2 Spike messages suppressed.
at the end of the simulation. This indicates that
spikes occurred during simulation, but we did not
request that they be reported.
h) Restore Tnum=0
Xpropagate Spike:
To check to see if the spike could cause problems with this
circuit, we will re-simulate with the spike propagate turned
back on. The "Restore Tnum=0" command directs SIMIC to
restart the simulation at its uninitialized state. The
"Xpropagate Spike:" command counteracts the previously
issued "No Xpropagate Spike:" command.
i) Simulate
Initiate re-simulation of the circuit. Notice that q1 went
to X at test #7, when the counter should go from count 3 to
4.
j) Restore Tnum=0
Break Memlatch:
Set up for another round of simulation. In this round,
we set a breakpoint whenever an X is latched into a
memory element (The T flip-flops in this circuit).
k) Simulate
Initiate simulation again. SIMIC stops and issues a
breakpoint message, that the flip-flop latched in an
X when the NS input (not-set) went X:
3 B 7> MEMLATCH CONDITION (NS AT 'X')[TNCF]: Q1
l) Restore Tnum=*
Trace List: Expand:
Instructs SIMIC to roll back to the start of this test
(previously stable point) with the Restore command.
Also, turn on activity tracing on all signals "Trace List:".
The "Expand:" option instructs SIMIC to include causality
information with the trace.
m) Simulate
Initiate simulation. Notice the event trace, "E", messages
followed by causality, "C" information.
Scanning the Trace information, we see that the master rank
of Q1 (Q1.1) went unknown, caused by SKIP_2 going unknown.
SKIP_2 went unknown because NQ1_Q2 went unknown, triggered
by NQ2 and Q1 changing too close for NQ1_Q1 to adequately
respond.
We have quickly and easily identified the problem. Notice
we are frozen at the breakpoint again. We can replay this
small piece of the simulation as many times as necessary
until the problem is isolated.
SIMIC has a large repertoire of interactive debugging tools.
Here are some you may want to try:
Display value of signal Q1:
Look List=Q1
Display value of signal CL4 and its input drivers:
Look Input: List=cl4
Display any signals in an unknown state:
Look X:
Display delays of all signals:
?Delay List:
Here are some other commands that are useful when
troubleshooting real designs:
Display charge storage value for signal A:
?Decay List=a
Display load values for signals B and C:
?Loading List=b,c
Checkpoint the simulation every 100 stable points:
Save Pstep=100
Stop simulation if signal D goes unknown:
Break X=d
Warn if any signal spikes.
Warn Spike:
There are many more options that make troubleshooting
large circuit easy in SIMIC.
n) Quit
Leave SIMIC session.