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Text File  |  1991-05-28  |  15KB  |  663 lines
  1.  
  2. /*    @(#)vga.xgi    3.2     9/8/89 16:30:29   */
  3.  
  4. /* ******************************************************************* *
  5.  *             XEGIA(tm) GrafInfo File for               *
  6.  *                                       *
  7.  *      Copyright (c) 1989 Metagraphics Software Corporation           *
  8.  *    269 Mount Hermon Road, PO 66779, Scotts Valley, CA 95066       *
  9.  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
  10.  *                                       *
  11.  * ******************************************************************* */
  12.  
  13. /* **************************************************************** */
  14. VENDOR     MXIC      "MXIC_VGA"
  15.  MODEL     VGA      "VGA"
  16.   CLASS  SVGA      "Super VGA"
  17.    MODE   800x600-16  "800x600 16 color"
  18.  
  19.       MEMORY(0xa0000,0x10000);          /* Base Address, Length         */
  20.       PORT(0x3c2,0x3ca,0x3cc,0x3da);  /* General/External registers  */
  21.       PORT(0x3c0,0x3c1);          /* Attribute             */
  22.       PORT(0x3c4,0x3c5);          /* Sequencer             */
  23.       PORT(0x3cE,0x3cF);          /* Graphics             */
  24.       PORT(0x3d4,0x3d5);          /* CRTC                 */
  25.  
  26. PROCEDURE InitGraphics
  27.     {
  28.  
  29.     DEVCLASS    = 0x55;
  30.     DEVTYPE     = 01;
  31.     DEVTECH     = 02;    /* VGA */
  32.     PIXBYTES    = 100;
  33.     PIXWIDTH    = 800;
  34.     PIXHEIGHT   = 600;
  35.     PIXRESX     = 64;
  36.     PIXRESY     = 54;
  37.     PIXBITS     = 1;
  38.     PIXPLANES   = 4;
  39.     MAPFLAGS    = 0;
  40.     BASEADDRESS = 0xA0000;
  41.     INTERLEAVE  = 1;
  42.     INTERSIZE   = 100;
  43.        }
  44.  
  45.  PROCEDURE   SetGraphics
  46.     {
  47.  
  48.     /* sequencer */
  49.     r0 = 0x1;   /* reset */
  50.     r1 = 0x1;
  51.     r2 = 0xF;
  52.     r3 = 0x0;
  53.     r4 = 0x6;
  54.     bout(5, 0x3c4, 0x3c5);
  55.  
  56.     /* misc output reg */
  57.     out(0x3c2,0x0f);
  58. /*
  59. IF    OSC EQ ENABLE
  60.     db    03h
  61. ENDIF
  62. IF    ICS EQ ENABLE
  63.     db    0fh
  64. ENDIF
  65. IF    MXCLK EQ ENABLE
  66.     db    0bh
  67. ENDIF
  68. */
  69.  
  70.     /* remove sequencer reset */
  71.     r0 = 0x3; bout(1,0x3c4,0x3c5);
  72.  
  73.     /* unprotect crtc regs 0-7 */
  74.     out(0x3d4, 0x11);  out(0x3d5, 0x0);
  75.  
  76.     /* crtc */
  77.     r0  = 0x7b; r1    = 0x63; r2  = 0x64; r3    = 0x9e;
  78.     r4  = 0x69; r5    = 0x8f; r6  = 0x6f; r7    = 0xf0;
  79.     r8  = 0;    r9    = 0x60; r10 = 0;    r11 = 0;
  80.     r12 = 0;    r13 = 0;    r14 = 0;    r15 = 0;
  81.     r16 = 0x58; r17 = 0x8e; r18 = 0x57; r19 = 0x32;
  82.     r20 = 0;    r21 = 0x58; r22 = 0x6f; r23 = 0xe3;
  83.     r24 = 0xff;
  84.     bout( 25, 0x3d4, 0x3d5 );
  85.  
  86.     /* graphics controller */
  87.     r0 = 0x0;
  88.     r1 = 0x0;
  89.     r2 = 0x0;
  90.     r3 = 0x0;
  91.     r4 = 0x0;
  92.     r5 = 0x0;
  93.     r6 = 0x5;
  94.     r7 = 0xf;
  95.     r8 = 0xff;
  96.     bout( 9, 0x3ce, 0x3cf );
  97.  
  98.     /* attribute controller */
  99.     in(r63,0x3da);     /* reset attribute F/F */
  100.  
  101.     /* palette */
  102.     r0  = 00;   r1    = 01;    r2  = 02;   r3    = 03;
  103.     r4  = 04;   r5    = 05;    r6  = 0x14; r7    = 07;
  104.     r8  = 0x38; r9    = 0x39; r10 = 0x3A; r11 = 0x3B;
  105.     r12 = 0x3C; r13 = 0x3D; r14 = 0x3E; r15 = 0x3F;
  106.  
  107.     /* attribute controller */
  108.     r16 = 01;    r17 = 00;    r18 = 0x0F;    r19 = 00;
  109.  
  110.     bout( 20, 0x3C0, 0x3C0 );
  111.  
  112.     /* palette mask */
  113.     out( 0x3C6, 0xFF);
  114.  
  115.     /* enable palette */
  116.     out( 0x3C0, 0x20);
  117.  
  118.     /* set extended registers */
  119.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  120.     out( 0x3c5, 0x87);
  121.  
  122.     out( 0x3c4, 0xc3);
  123.     out( 0x3c5, 0x20);    /* BUS16EN,CFD2,1,0,EXT256MD,SEGON     */
  124.                 /* BUS16EN bit should be read back first */
  125.     out( 0x3c4, 0xc4);
  126.     out( 0x3c5, 0);
  127. /*
  128. IF    OSC EQ ENABLE
  129.     dw    02c4h
  130. ENDIF
  131. IF    ICS EQ ENABLE
  132.     dw    00c4h
  133. ENDIF
  134. IF    MXCLK EQ ENABLE
  135.     dw    01c4h
  136. ENDIF
  137. */
  138.     out(0x3c2,0x0f);
  139. /*
  140. IF    OSC EQ ENABLE
  141.     db    03h
  142. ENDIF
  143. IF    ICS EQ ENABLE
  144.     db    0fh
  145. ENDIF
  146. IF    MXCLK EQ ENABLE
  147.     db    0bh
  148. ENDIF
  149. */
  150.  
  151.     out( 0x3c4, 0xf0);
  152.     out( 0x3c5, 0);     /* EXTVGAMODE(0),MASKHIGH(0) */
  153.                 /* SYNCVIDEO(0),INTERLACE(0) */
  154.  
  155.     }
  156.  
  157.     PROCEDURE SetText
  158.      {
  159.  
  160.      /* unprotect crtc regs 0-7 */
  161.      out( 0x3D4,0x11);   out(0x3D5,0x20);
  162.  
  163.      in(r63,0x3DA);           /* reset attr F/F */
  164.      out(0x3C0,0);              /* disable palette */
  165.  
  166.  
  167.      r0 = 0x01;  r1 = 0x00;  r2 = 0x03;  r3 = 0x00;  r4 = 0x02;
  168.      bout( 5, 0x3C4, 0x3C5 )      /* sequencer regs */
  169.  
  170.      out(0x3C2,0x67);          /* misc out reg   */
  171.  
  172.  
  173.      r0=0x03; bout(1,0x3C4,0x3C5);      /* sequencer enable */
  174.  
  175.  
  176.      /* unprotect crtc regs 0-7 */
  177.      out(0x3D4, 0x11);  out(0x3D5, 0x20);
  178.  
  179.      r0  = 0x5F;  r1  = 0x4F;  r2  = 0x50;    r3  = 0x82; /* crtc */
  180.      r4  = 0x55;  r5  = 0x81;  r6  = 0xBF;    r7  = 0x1F;
  181.      r8  = 0x00;  r9  = 0x4F;  r10 = 0x0D;    r11 = 0x0E;
  182.      r12 = 0x00;  r13 = 0x00;  r14 = 0x00;    r15 = 0x00;
  183.      r16 = 0x9C;  r17 = 0x8E;  r18 = 0x8F;    r19 = 0x28;
  184.      r20 = 0x1F;  r21 = 0x96;  r22 = 0xB9;    r23 = 0xA3;
  185.      r24 = 0xFF;  bout(25,0x3D4,0x3D5);
  186.  
  187.      out(0x3CC,0x00); out(0x3CA,0x01); /* graphics controller */
  188.      r0  = 0x00;  r1  = 0x00;  r2  = 0x00;    r3  = 0x00;
  189.      r4  = 0x00;  r5  = 0x10;  r6  = 0x0E;    r7  = 0x00;
  190.      r8  = 0xFF;  bout(9,0x3CE,0x3CF);
  191.  
  192.      in(r63,0x3DA);           /* reset attr F/F */
  193.  
  194.      r0  = 0x00;  r1  = 0x01;  r2  = 0x02;    r3  = 0x03; /* palette      */
  195.      r4  = 0x04;  r5  = 0x05;  r6  = 0x14;    r7  = 0x07;
  196.      r8  = 0x38;  r9  = 0x39;  r10 = 0x3A;    r11 = 0x3B;
  197.      r12 = 0x3C;  r13 = 0x3D;  r14 = 0x3E;    r15 = 0x3F;
  198.      r16 = 0x0C;  r17 = 0x00;  r18 = 0x0F;    r19 = 0x08; /* attr cntlr */
  199.      bout(20,0x3C0,0x3C0);
  200.  
  201.      out(0x3C0,0x20);          /* enable palette */
  202.  
  203.     /* set extended registers */
  204.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  205.     out( 0x3c5, 0x87);
  206.  
  207.     out( 0x3c4, 0xc3);
  208.     out( 0x3c5, 0xa0);
  209.  
  210.     out( 0x3c4, 0xc4);
  211.     out( 0x3c5, 0xc0);
  212.  
  213.     out(0x3C2,0x67);
  214.  
  215.     out( 0x3c4, 0xf0);
  216.     out( 0x3c5, 0);
  217.  
  218.      }
  219.  
  220.  
  221. /* **************************************************************** */
  222.  
  223. VENDOR     MXIC      "MXIC_VGA"
  224.  MODEL     VGA      "VGA"
  225.   CLASS  SVGA      "Super VGA"
  226.    MODE   1024x768i-16    "1024x768i 16 color"
  227.  
  228.  
  229. /*  for interlaced monitor only */
  230.  
  231.       MEMORY(0xa0000,0x20000);          /* Base Address, Length         */
  232.       PORT(0x3c2,0x3ca,0x3cc,0x3da);  /* General/External registers  */
  233.       PORT(0x3c0,0x3c1);          /* Attribute             */
  234.       PORT(0x3c4,0x3c5);          /* Sequencer             */
  235.       PORT(0x3cE,0x3cf);          /* Graphics             */
  236.       PORT(0x3d4,0x3d5);          /* CRTC                 */
  237.       PORT(0X46e8,0x103);
  238.  
  239.  
  240. PROCEDURE InitGraphics
  241.     {
  242.  
  243.     DEVCLASS    = 0x56;
  244.     DEVTYPE     = 01;
  245.     DEVTECH     = 02;    /* VGA */
  246.     PIXBYTES    = 128;
  247.     PIXWIDTH    = 1024;
  248.     PIXHEIGHT   = 768;
  249.     PIXRESX     = 96;
  250.     PIXRESY     = 96;
  251.     PIXBITS     = 1;
  252.     PIXPLANES   = 4;
  253.     MAPFLAGS    = 0;
  254.     BASEADDRESS = 0xA0000;
  255.     INTERLEAVE  = 1;
  256.     INTERSIZE   = 128;
  257.       }
  258.  
  259. PROCEDURE   SetGraphics
  260.     {
  261.  
  262.     /* sequencer */
  263.     r0 = 0x1;   /* reset */
  264.     r1 = 0x1;
  265.     r2 = 0xF;
  266.     r3 = 0x0;
  267.     r4 = 0x6;
  268.     bout(5, 0x3c4, 0x3c5);
  269.  
  270.     /* misc output reg */
  271.     out(0x3c2,0x0f);
  272. /*
  273. IF    OSC EQ ENABLE
  274.     db    0fh
  275. ENDIF
  276. IF    ICS EQ ENABLE
  277.     db    07h
  278. ENDIF
  279. IF    MXCLK EQ ENABLE
  280.     db    0fh
  281. ENDIF
  282. */
  283.  
  284.     /* remove sequencer reset */
  285.     r0 = 0x3; bout(1,0x3c4,0x3c5);
  286.  
  287.     /* Feature Control registers */
  288.     out(0x3da, 0);
  289.  
  290.     /* unprotect crtc regs 0-7 */
  291.     out(0x3d4, 0x11);  out(0x3d5, 0x0);
  292.  
  293.     /* crtc */
  294.     r0  = 0x99; r1    = 0x7f; r2  = 0x81; r3    = 0x9b;
  295.     r4  = 0x83; r5    = 0x10; r6  = 0x9d; r7    = 0x1f;
  296.     r8  = 0;    r9    = 0x40; r10 = 0;    r11 = 0;
  297.     r12 = 0;    r13 = 0;    r14 = 0;    r15 = 0;
  298.     r16 = 0x84; r17 = 0x8c; r18 = 0x7f; r19 = 0x40;
  299.     r20 = 0;    r21 = 0x84; r22 = 0x98; r23 = 0xe3;
  300.     r24 = 0xff;
  301.     bout( 25, 0x3d4, 0x3d5 );
  302.  
  303.     /* graphics controller */
  304.     r0 = 0x0;
  305.     r1 = 0x0;
  306.     r2 = 0x0;
  307.     r3 = 0x0;
  308.     r4 = 0x0;
  309.     r5 = 0x0;
  310.     r6 = 0x1;
  311.     r7 = 0xf;
  312.     r8 = 0xff;
  313.     bout( 9, 0x3ce, 0x3cf );
  314.  
  315.  
  316.     /* attribute controller */
  317.     in(r63,0x3da);     /* reset f/f */
  318.  
  319.     /* palette */
  320.     r0  = 00;   r1    = 01;    r2  = 02;   r3    = 03;
  321.     r4  = 04;   r5    = 05;    r6  = 0x14; r7    = 07;
  322.     r8  = 0x38; r9    = 0x39; r10 = 0x3a; r11 = 0x3b;
  323.     r12 = 0x3c; r13 = 0x3d; r14 = 0x3e; r15 = 0x3f;
  324.  
  325.     /* attribute controller */
  326.     r16 = 01;    r17 = 00;    r18 = 0x0F;    r19 = 00;
  327.  
  328.     bout( 20, 0x3c0, 0x3c0 );
  329.  
  330.     /* palette mask */
  331.     out( 0x3c6, 0xff);
  332.  
  333.     /* enable palette */
  334.     out( 0x3c0, 0x20);
  335.  
  336.     /* set extended registers */
  337.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  338.     out( 0x3c5, 0x87);
  339.  
  340.     out( 0x3c4, 0xc3);
  341.     out( 0x3c5, 0x44);    /* BUS16EN,CFD2,1,0,EXT256MD,SEGON     */
  342.                 /* BUS16EN bit should be read back first */
  343.     out( 0x3c4, 0xc4);
  344.     out( 0x3c5, 0);
  345. /*
  346. IF    OSC EQ ENABLE
  347.     dw    00c4h
  348. ENDIF
  349. IF    ICS EQ ENABLE
  350.     dw    01c4h
  351. ENDIF
  352. IF    MXCLK EQ ENABLE
  353.     dw    00c4h
  354. ENDIF
  355. */
  356.     out(0x3C2,0x0f);
  357. /*
  358. IF    OSC EQ ENABLE
  359.     db    0fh
  360. ENDIF
  361. IF    ICS EQ ENABLE
  362.     db    07h
  363. ENDIF
  364. IF    MXCLK EQ ENABLE
  365.     db    0fh
  366. ENDIF
  367. */
  368.  
  369.     out( 0x3c4, 0xf0);
  370.     out( 0x3c5, 0x0b);    /* EXTVGAMODE(0),MASKHIGH(0) */
  371.                 /* SYNCVIDEO(0),INTERLACE(0) */
  372.  
  373.  
  374.     }
  375.  
  376.     PROCEDURE SetText
  377.      {
  378.  
  379.      /* unprotect crtc regs 0-7 */
  380.      out( 0x3d4,0x11);   out(0x3d5,0x20);
  381.  
  382.      in(r63,0x3da);           /* reset attr F/F */
  383.      out(0x3c0,0);              /* disable palette */
  384.  
  385.  
  386.      r0 = 0x01;  r1 = 0x00;  r2 = 0x03;  r3 = 0x00;  r4 = 0x02;
  387.      bout( 5, 0x3c4, 0x3c5 )      /* sequencer regs */
  388.  
  389.      out(0x3c2,0x67);          /* misc out reg   */
  390.  
  391.  
  392.      r0=0x03; bout(1,0x3c4,0x3c5);      /* sequencer enable */
  393.  
  394.  
  395.      /* unprotect crtc regs 0-7 */
  396.      out(0x3d4, 0x11);  out(0x3d5, 0x20);
  397.  
  398.      r0  = 0x5f;  r1  = 0x4f;  r2  = 0x50;    r3  = 0x82; /* crtc */
  399.      r4  = 0x55;  r5  = 0x81;  r6  = 0xbf;    r7  = 0x1f;
  400.      r8  = 0x00;  r9  = 0x4f;  r10 = 0x0d;    r11 = 0x0e;
  401.      r12 = 0x00;  r13 = 0x00;  r14 = 0x00;    r15 = 0x00;
  402.      r16 = 0x9c;  r17 = 0x8e;  r18 = 0x8f;    r19 = 0x28;
  403.      r20 = 0x1f;  r21 = 0x96;  r22 = 0xb9;    r23 = 0xa3;
  404.      r24 = 0xff;
  405.      bout(25,0x3d4,0x3d5);
  406.  
  407.      out(0x3cc,0x00); out(0x3ca,0x01); /* graphics controller */
  408.      r0  = 0x00;  r1  = 0x00;  r2  = 0x00;    r3  = 0x00;
  409.      r4  = 0x00;  r5  = 0x10;  r6  = 0x0e;    r7  = 0x00;
  410.      r8  = 0xff;  bout(9,0x3ce,0x3cf);
  411.  
  412.      in(r63,0x3da);           /* reset attr F/F */
  413.  
  414.      r0  = 0x00;  r1  = 0x01;  r2  = 0x02;    r3  = 0x03; /* palette      */
  415.      r4  = 0x04;  r5  = 0x05;  r6  = 0x14;    r7  = 0x07;
  416.      r8  = 0x38;  r9  = 0x39;  r10 = 0x3a;    r11 = 0x3b;
  417.      r12 = 0x3c;  r13 = 0x3d;  r14 = 0x3e;    r15 = 0x3f;
  418.      r16 = 0x0c;  r17 = 0x00;  r18 = 0x0f;    r19 = 0x08; /* attr cntlr */
  419.      bout(20,0x3c0,0x3c0);
  420.  
  421.      out(0x3C0,0x20);          /* enable palette */
  422.  
  423.     /* set extended registers */
  424.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  425.     out( 0x3c5, 0x87);
  426.  
  427.     out( 0x3c4, 0xc3);
  428.     out( 0x3c5, 0xa0);
  429.  
  430.     out( 0x3c4, 0xc4);
  431.     out( 0x3c5, 0xc0);
  432.  
  433.     out(0x3C2, 0x67);
  434.  
  435.     out( 0x3c4, 0xf0);
  436.     out( 0x3c5, 0);
  437.  
  438.      }
  439.  
  440.  
  441. /* **************************************************************** */
  442.  
  443. VENDOR     MXIC      "MXIC_VGA"
  444.  MODEL     VGA      "VGA"
  445.   CLASS  SVGA      "Super VGA"
  446.    MODE   1024x768n-16    "1024x768n 16 color"
  447.  
  448.  
  449. /*  for interlaced monitor only */
  450.  
  451.       MEMORY(0xa0000,0x20000);          /* Base Address, Length         */
  452.       PORT(0x3c2,0x3ca,0x3cc,0x3da);  /* General/External registers  */
  453.       PORT(0x3c0,0x3c1);          /* Attribute             */
  454.       PORT(0x3c4,0x3c5);          /* Sequencer             */
  455.       PORT(0x3cE,0x3cf);          /* Graphics             */
  456.       PORT(0x3d4,0x3d5);          /* CRTC                 */
  457.       PORT(0X46e8,0x103);
  458.  
  459.  
  460. PROCEDURE InitGraphics
  461.     {
  462.  
  463.     DEVCLASS    = 0x56;
  464.     DEVTYPE     = 01;
  465.     DEVTECH     = 02;    /* VGA */
  466.     PIXBYTES    = 128;
  467.     PIXWIDTH    = 1024;
  468.     PIXHEIGHT   = 768;
  469.     PIXRESX     = 96;
  470.     PIXRESY     = 96;
  471.     PIXBITS     = 1;
  472.     PIXPLANES   = 4;
  473.     MAPFLAGS    = 0;
  474.     BASEADDRESS = 0xa0000;
  475.     INTERLEAVE  = 1;
  476.     INTERSIZE   = 128;
  477.       }
  478.  
  479. PROCEDURE   SetGraphics
  480.     {
  481.  
  482.     /* sequencer */
  483.     r0 = 0x1;   /* reset */
  484.     r1 = 0x1;
  485.     r2 = 0xf;
  486.     r3 = 0x0;
  487.     r4 = 0x6;
  488.     bout(5, 0x3c4, 0x3c5);
  489.  
  490.     /* misc output reg */
  491.     out(0x3c2,0x0b);
  492. /*
  493. IF    OSC EQ ENABLE
  494.     db    0bh
  495. ENDIF
  496. IF    ICS EQ ENABLE
  497.     db    0bh
  498. ENDIF
  499. IF    MXCLK EQ ENABLE
  500.     db    0fh
  501. ENDIF
  502. */
  503.  
  504.     /* remove sequencer reset */
  505.     r0 = 0x3; bout(1,0x3c4,0x3c5);
  506.  
  507.     /* Feature Control registers */
  508.     out(0x3da, 0);
  509.  
  510.     /* unprotect crtc regs 0-7 */
  511.     out(0x3d4, 0x11);  out(0x3d5, 0x0);
  512.  
  513.     /* crtc */
  514.     r0  = 0xa2; r1    = 0x7f; r2  = 0x80; r3    = 0x85;
  515.     r4  = 0x87; r5    = 0x90; r6  = 0x2c; r7    = 0xfd;
  516.     r8  = 0;    r9    = 0x60; r10 = 0;    r11 = 0;
  517.     r12 = 0;    r13 = 0;    r14 = 0;    r15 = 0;
  518.     r16 = 0x0f; r17 = 0x8c; r18 = 0xff; r19 = 0x40;
  519.     r20 = 0;    r21 = 0x07; r22 = 0x26; r23 = 0xe3;
  520.     r24 = 0xff;
  521.     bout( 25, 0x3d4, 0x3d5 );
  522.  
  523.     /* graphics controller */
  524.     r0 = 0x0;
  525.     r1 = 0x0;
  526.     r2 = 0x0;
  527.     r3 = 0x0;
  528.     r4 = 0x0;
  529.     r5 = 0x0;
  530.     r6 = 0x1;
  531.     r7 = 0xf;
  532.     r8 = 0xff;
  533.     bout( 9, 0x3ce, 0x3cf );
  534.  
  535.  
  536.     /* attribute controller */
  537.     in(r63,0x3da);     /* reset f/f */
  538.  
  539.     /* palette */
  540.     r0  = 00;   r1    = 01;    r2  = 02;   r3    = 03;
  541.     r4  = 04;   r5    = 05;    r6  = 0x14; r7    = 07;
  542.     r8  = 0x38; r9    = 0x39; r10 = 0x3a; r11 = 0x3b;
  543.     r12 = 0x3c; r13 = 0x3d; r14 = 0x3e; r15 = 0x3f;
  544.  
  545.     /* attribute controller */
  546.     r16 = 01;    r17 = 00;    r18 = 0x0F;    r19 = 00;
  547.  
  548.     bout( 20, 0x3c0, 0x3c0 );
  549.  
  550.     /* palette mask */
  551.     out( 0x3c6, 0xff);
  552.  
  553.     /* enable palette */
  554.     out( 0x3c0, 0x20);
  555.  
  556.     /* set extended registers */
  557.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  558.     out( 0x3c5, 0x87);
  559.  
  560.     out( 0x3c4, 0xc3);
  561.     out( 0x3c5, 0x54);    /* BUS16EN,CFD2,1,0,EXT256MD,SEGON     */
  562.                 /* BUS16EN bit should be read back first */
  563.     out( 0x3c4, 0xc4);
  564.     out( 0x3c5, 1);
  565. /*
  566. IF    OSC EQ ENABLE
  567.     dw    00c4h
  568. ENDIF
  569. IF    ICS EQ ENABLE
  570.     dw    01c4h
  571. ENDIF
  572. IF    MXCLK EQ ENABLE
  573.     dw    01c4h
  574. ENDIF
  575. */
  576.     out(0x3C2,0x0b);
  577. /*
  578. IF    OSC EQ ENABLE
  579.     db    0bh
  580. ENDIF
  581. IF    ICS EQ ENABLE
  582.     db    0bh
  583. ENDIF
  584. IF    MXCLK EQ ENABLE
  585.     db    0fh
  586. ENDIF
  587. */
  588.  
  589.     out( 0x3c4, 0xf0);
  590.     out( 0x3c5, 0x08);    /* EXTVGAMODE(0),MASKHIGH(0) */
  591.                 /* SYNCVIDEO(0),INTERLACE(0) */
  592.  
  593.  
  594.     }
  595.  
  596.     PROCEDURE SetText
  597.      {
  598.  
  599.      /* unprotect crtc regs 0-7 */
  600.      out( 0x3d4,0x11);   out(0x3d5,0x20);
  601.  
  602.      in(r63,0x3da);           /* reset attr F/F */
  603.      out(0x3c0,0);              /* disable palette */
  604.  
  605.  
  606.      r0 = 0x01;  r1 = 0x00;  r2 = 0x03;  r3 = 0x00;  r4 = 0x02;
  607.      bout( 5, 0x3c4, 0x3c5 )      /* sequencer regs */
  608.  
  609.      out(0x3c2,0x67);          /* misc out reg   */
  610.  
  611.  
  612.      r0=0x03; bout(1,0x3c4,0x3c5);      /* sequencer enable */
  613.  
  614.  
  615.      /* unprotect crtc regs 0-7 */
  616.      out(0x3d4, 0x11);  out(0x3d5, 0x20);
  617.  
  618.      r0  = 0x5f;  r1  = 0x4f;  r2  = 0x50;    r3  = 0x82; /* crtc */
  619.      r4  = 0x55;  r5  = 0x81;  r6  = 0xbf;    r7  = 0x1f;
  620.      r8  = 0x00;  r9  = 0x4f;  r10 = 0x0d;    r11 = 0x0e;
  621.      r12 = 0x00;  r13 = 0x00;  r14 = 0x00;    r15 = 0x00;
  622.      r16 = 0x9c;  r17 = 0x8e;  r18 = 0x8f;    r19 = 0x28;
  623.      r20 = 0x1f;  r21 = 0x96;  r22 = 0xb9;    r23 = 0xa3;
  624.      r24 = 0xff;
  625.      bout(25,0x3d4,0x3d5);
  626.  
  627.      out(0x3cc,0x00); out(0x3ca,0x01); /* graphics controller */
  628.      r0  = 0x00;  r1  = 0x00;  r2  = 0x00;    r3  = 0x00;
  629.      r4  = 0x00;  r5  = 0x10;  r6  = 0x0e;    r7  = 0x00;
  630.      r8  = 0xff;  bout(9,0x3ce,0x3cf);
  631.  
  632.      in(r63,0x3da);           /* reset attr F/F */
  633.  
  634.      r0  = 0x00;  r1  = 0x01;  r2  = 0x02;    r3  = 0x03; /* palette      */
  635.      r4  = 0x04;  r5  = 0x05;  r6  = 0x14;    r7  = 0x07;
  636.      r8  = 0x38;  r9  = 0x39;  r10 = 0x3a;    r11 = 0x3b;
  637.      r12 = 0x3c;  r13 = 0x3d;  r14 = 0x3e;    r15 = 0x3f;
  638.      r16 = 0x0c;  r17 = 0x00;  r18 = 0x0f;    r19 = 0x08; /* attr cntlr */
  639.      bout(20,0x3c0,0x3c0);
  640.  
  641.      out(0x3C0,0x20);          /* enable palette */
  642.  
  643.     /* set extended registers */
  644.     out( 0x3c4, 0xa7);        /* unlock extended registers */
  645.     out( 0x3c5, 0x87);
  646.  
  647.     out( 0x3c4, 0xc3);
  648.     out( 0x3c5, 0xa0);
  649.  
  650.     out( 0x3c4, 0xc4);
  651.     out( 0x3c5, 0xc0);
  652.  
  653.     out(0x3C2, 0x67);
  654.  
  655.     out( 0x3c4, 0xf0);
  656.     out( 0x3c5, 0);
  657.  
  658.      }
  659.  
  660.  
  661. /* End of File - VGA.XGI */
  662.  
  663.