ftp.whtech.com/ftp.whtech.com.tar/ftp.whtech.com/Geneve/9640news/CAT14/RS232.ARK

Text File | 2006-10-19 | 17KB | 526 lines

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RS232 Tutorial written By Mack McCormick


     Many people have asked me to
explain in better detail how they can
directly access the RS232 ports on their
99/4As for such things as terminal
emulators, BBS Software, protocol file
transfer software, and so on. Many of
these people have made some attempt at
trying to do single byte I/O using the
standard DSR entries but soon get
frustrated with the hassle that is
involved, not to mention the lack of
ability to tell when a character has
arrived at the port, detecting carrier
and ringing signals and other such
useful features. In this article we will
give you an overview of the TMS 9902
Asynchronous Communications Controller
Chip used in the TI RS232 Card and
define the input CRU testing bits; the
final article will explain the details
of programming the 9902 directly with
some code examples.

      TMS 9902 Overview. Figure 1 shows
the pinout of the TMS 9902 ACC Chip. The
9902 is fabricated using NMOS and uses
standard TTL level signals on all inputs
and outputs. The device is capable of
handling asynchronous communications
with word lengths from 5 to 8 bits with
1, 1 1/2 and 2 stop bits, full parity
checking (even/odd/none) with built in
data rate generation (no external bit
rate generators required) up to 19,200
bits per second. The 9902 also includes
an interval timer with resolution from
64 to 16,320 microseconds. Interfacing
between the 9902 and the 9900 host
environment is done thru the
Communications Register Unit, the CRU.
As you look at Figure 1 you see S0-S4,
these are the CRU address lines that are
used to interface the 9902 to any 9900
series microprocessor. When the chip
enable (pin 17) is asserted the 9902 is
placed on the bus and the function
requested is determined by S0-S4 and the
CRU control logic. CRUCLK (pin 15)
provides the CRU timing while the system
clock (pin 16) provides the timing for
the rest of the 9902. CRUIN (pin 4) and
CRUOUT (pin 8) are the CRU input and
output bits, respectively. In addition
to the CRU logic additional lines are
provided for Request To Send (pin 5),
Clear To Send (pin 6) and Data Set Ready
(pin 7.) The received data is on pin 3,
the transmitted data is sent out over on
pin 2, and the interrupt line for the
9902 is on pin 1. Finally, +5 volts goes
on pin 18 and logic zero (ground) is on
pin 9. For RS232 applications the widely
used 75188/75189 buffer chips are used
for bringing out the transmit/receive
signals, as well as DSR, RTS and CTS. In
the 99/4A RTS and CTS are tied
together.

The interrupt pin will go to a low logic
level when certain conditions occur
during the operation of the 9902, these
will be explained shortly.

      TMS 9902 CRU Input Assignments.
Accessing the 9902 in your program
requires the use of assembly language
with the CRU instructions TB, SBO, SBZ,
LDCR and STCR; check your Assembly
Language reference manual for the format
of the instructions. Table 1 shows the
input bit assignments which goes as
follows:

 Bit 31: Interrupt. When programmed, any
of the following conditions, if met;
will set this bit and also cause the
interrupt pin on the 9902 to be
asserted: DSCINT, TIMINT, XBINT, RBINT.
In addition, the respective bit that
raised this condition will also be set.

 Bit 30: Flag. Set when any of the load
register commands are issued or when the
break bit is set (See Table 2.)

 Bit 29: Data Set Status Change. Set
when DSR or CTS changes logic states and
is stable for 2 clock cycles. This bit
is cleared when an output to bit 21
(DSCENB) is made.
 Bit 28: Clear To Send. Indicates the
logic level on the Clear To Send pin.
Note that the bit present will be the
inverse of the logic level on the pin.

 Bit 27: Data Set Ready. Indicates the
logic level on the Data Set Ready pin.
The bit will be inverse of the input.
 Bit 26: Request To Send. Indicates the
logic level of the Request To Send pin.
The bit will be the inverse of the pin.

 Bit 25: Timer Elapsed. Set when the
timer register equals zero. Cleared by
an output to bit 20 (TIMENB).

 Bit 24: Timer Error. This bit is set
when the timer has reached zero and when
TIMELP is set. This is raised when the
software fails to recognize TIMELP and
reset it before another interval passed.
This is also cleared by an output to bit
20.

 Bit 23: Transmitter Shift Register

 Empty. Set when the Transmitter shift
register is not sending data (also
indicates that XOUT is at a high logic
level.) When this bit is at logic zero,
character transmission is in progress.

 Bit 22: Transmit Buffer Register Empty.
When set, this indicates that there is
not a character waiting to be
transmitted. It is set to a logic zero
when a character is written to the
transmit buffer register.

 Bit 21: Receive Buffer Register Loaded.
When set, indicates that a complete
character has been assembled in the
receive buffer register. It is cleared
by an output to bit 18 (RIENB).

 Bit 20: Data Set Status Change

 Interrupt. Set when either DSR or CTS
changes state and the Data Set Status
Interrupt has been enabled.
 Bit 19: Timer Interrupt. Set when the
timer has elapsed and the Timer
Interrupt has been enabled.

 Bit 17: Transmitter Interrupt. Set when
the Transmit buffer register is empty
and the Transmitter Interrupt has been
enabled.

 Bit 16: Receive Interrupt. Set when the
Receive Buffer register is loaded and
the receive interrupt has been enabled.

 Bit 15: Receive Input. The logic level
of the RIN line at the time that the
inpu was sampled.

 Bit 14: Receive Start Bit Detect. Set
during transition of the first bit of a
word. Normally not used.

 Bit 13: Receive Full Bit Detect. Set
when the first bit of the character
(excluing the start bit) is received,
and is cleared when the character is
completed. Not normally used.

 Bit 12: Receive Framing Error. Set when
the stop bit of the recived character is
a logic zero (should be a logic one),
indicating a transmission error. Reset
when a character with a correct stop bit
is received. It is recommended that this
bit only be sampled when RBRL is set.

 Bit 11: Receive Overrun Error. Set when
another character is being assembled in
the 9902 and the previous characeter has
not been acquired from the 9902 by the
software and the RBRL flag reset.

 Bit 10: Receive Parity Error. Set when
the parity of the incoming character is
incorrect, indicating transmission
error. Reset when a character with
correct parity is processed.

 Bit 9: Receive Error. Set when RFER,
ROVER, or RPER is set.

 Bits 7-0: Receive Buffer Register. This
is the register where the received
character is stored. For data lengths
shorter than eight bits the data is
right-justified in the register.

     In the last issue we covered the
Input CRU bit assignments of the TMS
9902 Asynchronous Communications
Controller Chip. In this part we will
cover the Output CRU Bit assignemnts,
programming examples and the TMS 9902 in
the TI 99/4A environment.

      CRU Output Bit Assignments (Also
see Table 2.) Described below are the
Output CRU Bit assignments and their
function:

 Bit 31: Reset. Setting this bit high
causes the 9902 to reset the entire
chip. All interrupts are disabled, RTS
is set high, all register flags (LDCTRL,
LDIR, LRDR, LXDR) are set high and the
BREAK flag is reset. No operation to the
TMS 9902 should be performed for 11
clock cycles after setting this bit.

 Bits 30-22: Not used.

 Bit 21: Data Set Change Interrupt

 Enable. Setting this bit causes the
9902 to generate an interrupt when input
bit 29 (Data Set Status Change) is set.
Resetting this bit disables the DSCH
interrupt. Writing any value to this bit
will reset input bit 29.

 Bit 20: Timer Interrupt Enable. Setting
this bit causes the 9902 to generate an
interrupt when TIMELP (Input bit 25) is
set. Resetting this bit disables the
TIMELP interrupts. Writing any value to
this bit will reset input bit 25.

 Bit 19: Transmit Buffer Interuupt

 Enable. Setting this bit causes the
9902 to generate an interrupt when XBRE
(input bit 22) is set. Resetting this
bit disables XBRE interrupts. This bit
dos not affect the current value of
XBRE.

 Bit 18: Receiver Interrupt Enable.
Setting this bit causes the 9902 to
generate an interrupt when RBRL (input
bit 21) is set. Resetting this bit
disables RBRL interrupts. Wrtiing any
value to this bit causes RBRL to reset.

 Bit 17: Break On. Setting this bit
causes the XOUT line to go to logic zero
whenever the transmitter is active and
XBR and XSR (both transmitter buffer and
shift registers) are empty and inhibits
loading characters into the transmit
buffer register. Resetting this bit
causes the transmitter to return to
normal operation.

 Bit 16: RTS On. Setting this bit causes
the RTS handshake signal to be active
(low.) Resetting this bit causes RTS to
go high after XSR and XBR are empty and
BRKON is reset. (RTS will not go
inactive until a character has completed
tansmission.)

 Bit 15: Test Mode. Setting this bit
causes RTS to be internally connected to
CTS, XOUT to RIN, DSR held internally
low, and the interval timer to operate
at 32 times its normal rate. This is
useful for debugging programs that are
transmitting and receiving data and for
tsting to insure that the internal 9902
functions are working properly.
Resetting this bit causes the 9902 to
return to normal operating mode.

 Bits 14-11: Register Load Control
 Flags. These bits are described below:

 Bit 14: Load Control Register. This bit
when set (either explicitly or after the
RESET bit is set) causes the control
regiter in bits 0-7 to be loaded into
the 9902. Resetting this bit (or upon
reception of the last control register
bit) causes the control register to be
inhibited from loading.
 Bit 13: Load Interval Register. Setting
this bit causes the next 8 bits (bits
0-7) to be loaded into the 9902's
interval register. the Bit is reset when
the last data bit is loaded or a logic
zeo is written to LDIR. To load this
regiter, LDCTRL must be reset (See Table
3.)

 Bit 12: Load Receive Data Rate Register.
Setting this bit causes the next 11 bits
(0-10) to be loaded into the 9902's
Receive data rate register. The bit is
reset when the last data bit is loaded
or a lofic zero is written to LRDR. To
load this register LDCTRL and LDIR must
be zero.

 bit 11:Load Transmit Data Rate Register.
Setting this bit causes the next 11 bits
(0-10) to be loaded into the 9902's
Transmit data rate register. The bit is
reset when the last data bit is loaded
or a logic zero is written to LXDR. To
load this register LDCTRL and LDIR must
be zero.

 Note: If both the transmit and receive
data rates are the same both registers
can be loaded simultaneously by setting
both LRDR and LXDR.

 Bits 10 thru 0: Data. Depending on the
control bits set data rate registers,
the interval register, the control
register or data to be transmitted are
written to these bits.

 The Control Register. The control
regiser is used to define the character
size, the parity of the word, the number
of stop bits and the operating frequency
of the 9902. Table 4 outlines the bit
positions and their settings. Of
importance is bit 3: for the /4A
environment this bit should always be
zero. The PENB bit determines if parity
checking is done, if set parity checking
is done; if reset no parity checking is
done. The PODD bit determines if the
9902 will check for/generate odd parity;
if set odd parity is processed; if reset
even parity is processed.

 The Data Rate Registers. Both receive
and transmit registers share the same
format. The data rate registers are
basically 2 programmable counters that
divide the system clock depending on the
bit settings in the counters to derive
the data rate. The first counter is a
divide by eight counter that is active
if bit 10 of the data rate register is
loaded. Since the internal 9902 clock
frequency is 1 MHz, setting this bit
causes its output to be 125KHz, while
resetting this bit passes the system
clock right thru. The output of this
first counter is fed into a 10-bit
counter and is further divided down by a
value from 0 to 1023. The output from
this counter is actually twice the data
rate (interval for half the bit period.)
so this output is divided by 2 to get
the actual data rate. Since this formula
is not exactly the asiest way to get the
baud rate, here's a list of the more
popular speeds and their register values
for your use:



    Speed            Hex Value

    =====            =========



    110 bps          >400 + >238

    300 bps          >400 + >0D0

    600 bps                 >341

   1200 bps                 >1A1

   2400 bps                 >0D0

   4800 bps                 >068

   9600 bps                 >034



(Note the >400 is the divide by 8
counter enable. If you need an oddball
baud rate, the formula is below:







    F     =      Fint (1 MHz)

            --------------------------
     bps      2 * (D9-D0) * (8 D10)


where D9-D0 is from 0 to 1023 and D10 is
the divide by eight counter.)



 The Interval Register. The Interval
register is a 8-bit counter which is
decremented every 64 clock cycles. When
the interval counter reches zero, the
appropraite interval register flags are
set and if interval interrups have been
enables the 9902 will generate an
interrupt. Taking into account the
register size the interval counter has
resolution from 64 to 16,320
microseconds in 64 microsecond
increments.

 Programming The TMS9902. This seems
like an awful lot of stuff to swallow in
order to program the 9902 but in reality
a lot of the nasty things are done for
you by the chip, so now lets look at
some code examples, but first we need to
know something about the way the 9902 is
addressed in the /4A environment.

Most of you who have gotten the
disassembly listing of the RS232 DSR
know that the DSR code is at CRU address
>1300. The 9902 themselves are at +>40
for the first 9902 and the second is at
+>80, so the values used for 9902
accesses are >1340 and >1380. If you
have the additonal RS232 card its CRU
offset is >1500 and the 9902s are also
+>40 and >+80. Its suggested that when
you code your routines you have a
subroutne which sets up the base address
to turn the DSR on and then adjusts R12
to access the proper 9902.

 Interrupts in the RS232 DSR. Tracing
thru the disassembly listing reveals
that during an interrupt request from
the RS232 DSR it determines the device
which fired the interrupt and determines
if a character was received. If a
character was not received it RESETS the
9902--so be careful how you program
the 9902 in the /4A environment. As a
side benefit tho, if you use interrupts
the DSR provides you with a mechanism of
getting incoming characters and
buffering them. Carefully trace the
interrupt code and you'll find that
>8300 contains a VDP address and >8302
an >8304 are pointers that are
manipulated to place characters into a
queue in VDR RAM.

 Example. To give you an idea of what
goes on with the 9902, Assembly source
code is being provided that shows how
the 9902 is initialized and how
characters are transmitted and received.
The program is the infamous T99 dumb

terminal emulator I wrote over a year
ago that uses the first RS232 port for
a modem running at 300 baud, 1 stop bit
and even parity with a printer attached
off of port 2 running at 9600 bps at odd
parity and 1 stop bit. The printer is
turned on by receipr of a control R and
is shut off by receipt of a control T.
This code also shows you some of the
things that are involved in writing a
terminal emulator and can serve as a
basis for writing more powerful
emulators. (the T99 source code can be
found in DL2 in the file T99.ASM.)

 Summary. There is still a lot of things
that we didn't cover in regards to the
9902 but with the information we have
provided here you should be in a good
postion to do some exploring on your
own; such as using one or two of the
control lines to hook up with modems
that provide auto-answer/auto-dial
capabilites and write a assembly program
to get you those features. The rest is
up to you and your imagination!

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