home *** CD-ROM | disk | FTP | other *** search
/ ftp.elysium.pl / ftp.elysium.pl.tar / ftp.elysium.pl / docs / schematics / computers / c64 / cpupla.gif < prev    next >
Graphics Interchange Format  |  2008-03-11  |  87.2 KB  |  1424x1856  |  1-bit (2 colors)
   ocr: U7 - 906107-01 6510 MICROPROCESSOR PIN ASSIGNMENT 1 01 Phase. 1 clock input. This clock input is RDY- Q1- 1 2 39 40-RES F02 used phase speeds. to 2 clock. develop 1 the MegHz internal or 2 MegHz overlapping IRO- 3 38 ERW 2 RDY Single step oparation input. A low applied NMI- 4 37-DBO will cause the processor to halt. The cur- AEC- 5 36-DB1 rent address line being fetched will be on VCC- 6 35 EDB2 the address bus. Can also be used to in- A0- - 7 34-DB3 terface slower devices to the micropro- A1- 8 331 FDB4 3 IRO cessor. Interrupt request input. When a law pulse A2- 9 32-DB5 is applied a jump to ...