ocr: COMMON I.C.'S (Continued) 7432 74S32 e 74LS32 e 74F32 QUAD 2-INPUT OR GATE PIN ASSIGNMENT LOGIC DIAGRAM TRUTH TABLE 14 vcc 13 INPUTS OUTPUT A B Y 12 L L 11j L H H H H 10 H H H H- HIGH volege level L= LOW vohage Invel GND E 2 B 7474 e 74S74 . 74LS74 DUAL D-TYPE FLIP FLOP (POSITIVE EDGE TRIGGERED) PIN ASSIGNMENT LOGIC DIAGRAM TRUTH TABLE Sp MODE INPUTS OUTPUTS OPERATING RDiS vcc 3, Rp CP D Q a 9, DRoz Asynchronous Asynchronous Set Reset H L H L X X X X H L L H CP, 2JD2 Ap (Clear) s0 MCP2 Load "1" Undetermined4l (Set) L H L H X 1 h X H H H L os Do)Ep2 Load "0" (Resat) H H I L H 4E Ploz Dos CF_ H- ...
