ocr: COMMON LINE DEFINITIONS A0-A7 PROCESSOR ADDRESS BUS LCA LOAD CONFIGURATION REGISTER AEC ADDRESS ENABLE CONTROL LP LIGHT PEN INPUT ATN ATTENTION LINE MAO-MA11 MULTIPLEXED ADDRESS BUS BA BUS AVAILABLE MMU MEMORY MANAGEMENT UNIT MS 0-4 MEMORY STATUS, ALSO INDENTIFIED AS C128/64 C128 OR C64 MODE ROMBANK CAP LK CAPITAL LOCK MUX ADDRESS MULTIPLEX CONTROL CAS DRAM COLUMN ADDRESS STROBE MEMORY MULTIPLEX CASENB RAM COLUMN ADDRESS STROBE ENABLE CASS SENSE CASSETTE SENSE NMI NON-MASKABLE INTERRUPT CASS WRT CASSETTE WRITE CASS MTR CASSETTE MOTOR PHI 0 2MHZ 0 CLOCK CHAROM CHARACTER ROM SELECT POT X.Y JOYST ...
