ocr: THE MEMORY MANAGEMENT UNIT (Continued) 1 VDD 5VDC input. 2 RESET System Heset. This input initializes internal 310389 3-10 TAB-TA15 registers Translated on a Address power up outputs. or Tri- hardware stated reset. fur 8722 MEMORY MANAGEMENT UNIT VIC cycles address during for AEC, use on provides the Multiplexed translated physical Address Bus and the Shared Static Bus. TA12 to TA15 are each defined to have an internal, depletion mode pullup with an equivalent resistance of 3.3K1 TA8 to TA11 each go tristate during VIC time (AEC low). VDD 1 48 SENSE40 11,12 CAS1 CASO. lines Column control Addr ...
