ocr: THE Z-80 MICROPROCESSOR (Continued) The Z-80 is designed to have explicit Read, Write and 1/O cycles, where an I/O cycle is distinct from a memory cycle. The 65xx family uses only memory mapped I/O and thus, for a 65xx bus, all V/O devices appear as memory locations, and all non-write cycles appear as read cycles. The Z-80 communicates cycle information via two control lines, the Read Enable and Write Enable lines. The C128 uses the Read Enable line of the Z-80 to gate the Processor Bus data to the Z-80 data bus. The Write Enable interfacing is somewhat more complicated. The Write Enable Circu ...
