home *** CD-ROM | disk | FTP | other *** search
/ ftp.elysium.pl / ftp.elysium.pl.tar / ftp.elysium.pl / docs / schematics / computers / c128 / manual / 05.gif < prev    next >
Graphics Interchange Format  |  2008-03-11  |  148.8 KB  |  2304x3300
   ocr: BUS ARCHITECTURE (Continued) During a VIC cycle, AEC low, the VIC chip address lines must be asserted. There is no completely separate address bus for the VIC addresses, sO it shares the VMAO VMA7 and TA8 - TA11 address lines that are otherwise tri-stated during AEC low. Most of the VIC addresses come out of the VIC chip already multiplexed, but two of them, VA6 and VA7. They do not supply column information, as the VIC chip supplies only fourteen bits of addressing. The higher order address bits VA14 and VA15 come from CIA 2, as in the C64. Thus, the VIC supplies complete VMAO - VMA7 for a VI ...