Meeting Pearls 1

home *** CD-ROM | disk | FTP | other *** search

/ Meeting Pearls 1 / Meeting Pearls Vol 1 (1994).iso / installed_progs / text / faqs / lsi-cad-faq.part3 < prev next >

Wrap

Internet Message Format | 1994-05-08 | 38.2 KB

Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 3/4) [LONG] Newsgroups: comp.lsi,comp.lsi.cad,news.answers,comp.answers From: altarrib@monk.ece.ucdavis.edu (Michael Altarriba) Date: Fri, 6 May 1994 22:11:55 GMT Archive-name: lsi-cad-faq/part3 The COSMOS package generates switch-level simulators for MOS circuits. The BDD package is a subset of COSMOS providing a set of library routines for symbolic Boolean manipulation. To obtain a copy of either COSMOS or BDD via FTP: 1. Create an appropriate subdirectory. For COSMOS, you may want to create a symbolic link /usr/cosmos to this directory, although this is not essential. 2. Connect to the subdirectory 3. FTP to n3.sp.cs.cmu.edu:usr/cosmos/ftp (login anonymous, password yourname@your.host.name) 4. Type: cd /usr/cosmos/ftp ls 5. Select which version of the code you want. The files are named bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver- sion number. Generally you should select the highest numbered ver- sion. 6. 6. Type: get <FILE> (where <FILE> is the file name of the selected ver- sion). get README quit 7. Follow the instructions in README 8. Send the following information to cosmos@cs.cmu.edu Your name Your postal address Your net address The file retrieved The date of your retrieval COSMOS and BDD are made available with the understanding that no part of it will be redistributed further without permission. Last updated 18 July 1991 by Derek Beatty. 27: ITEM (Taken from the item.news file contained in the package:) The first public release of ITEM, UCSC's logic minimizer using if-then- else DAGs, was made 2 January 1991. The system is available by anonymous ftp from ftp.cse.ucsc.edu:pbu/item/item.tar.Z . Also available are tech reports about the algorithms and data structures (88-28, 88-29, and 90- 43). ITEM can also be found at ftp.cse.ucsc.edu:pub/item directory. 28: PADS logic/PADS PCB: While this is a commercial product, they have just recently made avail- able a shareware version. This version is fully functional and indenti- cal to their schematic capture and PCB autoplace and route software except that it is limited to about 50 components. It is available for IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at several sites including wuarchive.wustl.edu:mirrors/msdos/cad/ (look for pads*.zip). There is a $50 registration fee if you would like to get future updates from them. 29: Another PCB Layout Package: (from Randy Nevin <randyn@microsoft.com>:) I'm distributing a freely-copyable software package to do autorouting of (1- and 2-layer) printed circuit boards on a PC or compatible. It is written in C (with a little .asm), and all source code is included. There is an autorouter, a board viewer, a rat nest viewer, and some output filters which generate postscript and hp laserjet output files. There is no charge, but I maintain the copyright (it is not public domain). If you want to read about it, I published an article on autorouting algorithms in the sept '89 dr. dobb's journal. ega is required (for the viewing pro- grams). If you'd like to get the software, send me a stamped, self- addressed floppy mailer and a floppy. I can handle 5.25" 360K or 1.2M, or 3.5" 1.4M, but if you send 360K there is some extra code that I won't be able to fit on the disk, so high density is better. I developed this software at home on my own time, and it is not related to what I do for my employer, so I will not use my employer's email resource to distribute it. however, it is available for anonymous ftp access on wsmr-simtel20.army.mil:PD1/<MSDOS.CAD>PCB.ARC , last I heard. I do not keep simtel up to date. But the version there is useable, and does include all source code. Randy Nevin 24135 SE 16th PL Issaquah, WA 98027 30: Magic (Current version 6.3): This is a polygon based lsi layout editor. It is capable of reading and writing magic, calma (version 3.0, corresponding to GDS II Release 5.1), and cif. It is available for anonymous ftp from gatekeeper.dec.com:/pub/DEC/magic . Linux versions of magic are available from the standard linux mirror archives, such as dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/ [128.6.18.15]: dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/magicp3-src.tar.gz , dorm.rutgers.edu:pub/linux/sources/usr.bin.X11/magic63p3-run.tar.gz 31: PSpice: This is a commercial product, however, they do have a student version that is available (limited to around 16 transistors). PC dos version: 5.0a: oak.oakland.edu:pub/msdos/electric/pspice5a.zip oak.oakland.edu:pub/msdos/electric/pspice5b.zip PC windows3 version 5.1: ftp.cica.indiana.edu:pub/pc/win3/util/pspice1.zip ftp.cica.indiana.edu:pub/pc/win3/util/pspice2.zip Mac version 5.1: sumex-aim.stanford.edu:info-mac/app/pspice-51.hqx The PC version is also available at a number of U.S. and non-U.S. sites. 32: Esim: A new version of the switch-level simulator ESIM that can handle CMOS transmission gates is available through MUG, ftp ftp.mosis.edu (128.9.0.32)) 33: Isplice3 (Current version 2.0): This is a high level simulator, I do not know much more then that. It is available via anonymous ftp from uicadb.csl.uiuc.edu. 34: Watand: (From Phil Munro <FC138001@ysub.ysu.edu>) This posting will give the interested person some information about the WATAND (WATerloo ANalysis and Design) circuit simulator. Watand was introduced at the 16th Midwest Symposium on Circuit Theory (1973). In spite of its lack of advertising, Watand still offers some advantages when compared with other well known circuit simulators. For example it is a *truly* interactive simulator; that is, one enters the "WATAND" environment in which analyses and design can be run and rerun, values changed, settings queried and changed, etc. Watand uses piecewise-linear as its primary simulation; other methods are optional. It has ten built-in analyses which include the standard dc, ac, and transient analyses, and two post-processors (display and discrete Fourier). Output may be in the form of printed tables; graphics display includes Tektronix 40xx output. At YSU interactive helps are also available. Watand provides for the creation and use of user defined elements in addition to its own good stock of 34 built-in elements plus 21 built-in user defined elements. User defined analyses and post-processors can also be written, and it includes a powerful macro facility. As of June, 1992, sale of the Watand simulator was still being handled by Mark O'Leavey, Waterloo Engineering Software, 22 King St. S., Suite 302, Waterloo, Ontario, CANADA, N2L 1C6, Fax: (519) 746-7931; Phone: (519) 741-8097. At that time I was informed that it was available only for DECStation and Sparcstation, although we are running it quite suc- cessfully at YSU under the CMS operation system on an Amdahl mainframe. Two new and helpful manuals are available for the simulator. They should be available at the Youngstown State University Bookstore, Youngs- town, OHio 44555: Their approximate cost should be $7 each: "WATAND Users Manual," by Dr. Phil Munro, Youngstown State University, April 1992, 233 pages, 10 chapters, 4 appendices, index. "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown State Unversity, June 1992, 204 pages, 12 chapters, index. Watand does *not* include digital simulation at this time, nor does it have any transmission-line elements. A self-heating BJT model has been developed and is proving useful. Monte Carlo statistical simulation is possible with dc and ac analyses using macro based analyses which have been developed at YSU. 35: Caltech VLSI CAD Tools: (From John Lazzaro <lazzaro@boom.CS.Berkeley.EDU>) Caltech VLSI CAD Tool Distribution We are offering to the Internet community a new revision of the Caltech electronic CAD system for analog VLSI neural networks. This distribution contains tools for schematic capture, netlist creation, and analog and digital simulation (log), IC mask layout, extraction, and DRC (wol), sim- ple chip compilation (wolcomp), MOSIS fabrication request generation (mosis), netlist comparison (netcmp), data plotting (view) and postscript graphics editing (until). These tools were used exclusively for the design and test of all the integrated circuits described in Carver Mead's book "Analog VLSI and Neural Systems". Until was used as the primary tool for figure creation for the book. The distribution also contains an example of an analog VLSI chip that was designed and fabricated with these tools, and an example of an Actel field-programmable gate array design that was simulated and converted to Actel format with these tools. These tools are distributed under a license very similar to the GNU license; the minor changes protect Caltech from liability. Highlights of the new revision includes: * Ports to new platforms (Supported platforms now include: Sun SPARC, Sun 3, HP Series 300/400/700/800, DEC MIPS-based Ultrix, Apple AU/X, linux, and IBM RS/6000 support). * Support for black and white displays, and resource database support for user preferences for sizing and placement of windows. New display modes in analog to support small screens. * Direct generation of SPICE netlists in analog, and new models for floating-well FET's, two-terminal devices with arbitrary i-v curves, and quantum-well tunnel diodes. * Many bug fixes for analog, wol, view, and until, and new features for view. If you are interested in some or all of these tools, 1) ftp to hobiecat.pcmp.caltech.edu:pub/chipmunk on the Internet, 2) log in as anonymous and use your username as the password 3) cd pub/chipmunk 4) copy the file README, that contains more information. European researchers can access these files through anonymous ftp using the machine ifi.uio.no in Norway; the files are in the directory chip- munk. We are unable to help users who do not have Internet ftp access. A small but rather important bug was found in the "analog" program of the new Chipmunk distribution announced several weeks ago -- a key MOS transistor parameter was off by an order of magnitude! The current copies of the distribution on hobiecat.caltech.edu and ifi.uio.no have this bug corrected; however, if you've already picked up and installed the distri- bution since the new release (early april), here are the directions for patching your current installation w/o bringing over and rebuilding the whole package: 1) anonymous ftp to hobiecat.pcmp.caltech.edu:pub/chipmunk 2) get the file models.cnf 3) in your distribution, use this file to replace log/lib/models.cnf That's it! Sorry for the inconvenience ... 36: Switcap2 (Current version 1.1): This is a switched capactor simulator. It is available from: SWITCAP Distribution centre, 411 Low Memorial Library, New York, N.Y. 10027. 37: Test Software based on Abramovici Text: (Contributed by Mel Breuer of the Univ. of Southern California) Many faculty are using the text by Abramovici, Breuer, and Fried- man entitled "Digital Systems Testing and Testable Design" in a class on testing. They have expressed an interest to supplement their course with software tools. At USC we have developed such a suite of tools. They include a good value simulator, fault simulator, fault col- lapsing module, and D-algorithm-based ATPG module for combinational logic. The software has been specifi- cally designed to be easily understood, modified and enhanced. The algorithms follow those described in the text. The software can be run in many modes, such as one module at a time, single step, interactively or as a batch process. Stu- dents can use the software "as is" to study the operation of the various algo- rithms, e.g. simulation of a latch using different delay models. Also, simple programming projects can be given, such as extend the simulator from a 3-valued system to a 5-valued system; or change the D-algorithm so that it only does single path sensiti- zation. There are literally over 50 interesting software enhancements that can be made by changing only a small part of the code. The system is written in C and runs on a SUN. If you are currently using the Abramovici text and would like a copy of this software, please send a message to Prof. Melvin Breuer at mb@poisson.usc.edu. 38: Test Generation and Fault Simulation Software (Contributed by Dr. Dong Ha of Virginia Tech) Two automatic test pattern generators (ATPGs) and a fault simula- tor for combinational circuits were developed at Virginia Tech, and the source codes of the tools are now ready for public release. ATLANTA is an ATPG for stuck-at faults. It is based on the FAN algorithm and a parallel-pattern, single-fault propaga- tion technique. It consists of optional sessions using random pattern testing, deterministic test pattern generation and test compaction. SOPRANO is an ATPG for stuck-open faults. The algo- rithm of SOPRANO is similar to ATLANTA except two consecutive patterns are applied to detect a stuck-open fault. FSIM is a parallel-pattern, single-fault simulator. All the tools are written in C. The source codes are fully commented, and README files contain user's manuals. Technical papers about the tools were presented at DAC-90 and ITC-91. All three tools are free to univer- sities. Companies are requested to make a contribution of $5000 but will have free technical assistance. For detailed in- formation, con- tact: Dr. Dong Ha Electrical Engineering Virginia Tech Blacksburg, VA 24061 TEL: 703-231-4942 FAX: 703-231-3362 dsha@vtvm1.cc.vt.edu 39: Olympus Synthesis System (From Rajesh K. Gupta <rgupta@sirius.Stanford.EDU>) Recently there have been several enquiries about the Olympus Synthesis System. Here are answers to some commonly asked questions. For details please send mail to "synthesis@chronos.stanford.edu". 1. What is Olympus Synthesis System? Olympus is a result of a continuing project on synthesis of digital cir- cuits here at Stanford University. Currently, Olympus synthesis system consists of a set of programs that perform synthesis tasks for synchro- nous, non-pipelined circuits starting from a description in a hardware description language, HardwareC. The output of synthesis is a technology independent netlist of gates. This netlist can be input to logic synthesis and technology mapping tools within Olympus or to UC Berkeley's mis/sis. Current technology mapping in Olympus is targeted for LSI logic standard cells and a set of PGA archi- tectures: Actel and Xilinx. 2. How is Olympus distributed? The source code and documentation for Olympus is distributed via ftp. 3. What are the system requirements for Olympus? Olympus has been tested on following hardware platforms: mips, sparc, hp9000s300, hp9000s800, hp9000s700, vax. All the programs in Olympus come with a default menu-driven ASCII interface. There is also a graphi- cal user interface, called "olympus", provided with the distribution. This interface is written using Motif procedures. You would need about 40 MBytes of disk space to extract and compile the system. 4. How can I obtain a copy of Olympus? Olympus is distributed free of charge by Stanford University. However, it is not available via anonymous ftp. In order to obtain a copy please send a mail to "olympus@chronos.stanford.edu" where an automatic-reply mailer would send instructions for obtaining Olympus software. 40: OASIS logic synthesis (From William R. Richards Jr. <richards@mcnc.org>) OASIS is a complete logic synthesis system based on the Logic3 HDL develped at MCNC (unfortunately neither VHDL or Verilog compatible). kk@mcnc.org is the person responsible for it. OASIS is available to US universities for $500 and non-US universities for $600. Industrial license is $3000. 41: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator (From William R. Richards Jr. <richards@mcnc.org>) CAzM is a Spice-like table-based analog circuit simulator. It offers sig- nificant performance advantages over other Berkeley Spice derivatives. It is used fairly extensively in our design community. US university license is $175, non-US $250. Commercial license is $800. It comes with an X11- based signal viewing tool Sigview which is public domain and may be anonymous ftp'd from mcnc.org. I am the primary contact for CAzM at MCNC. (From Bhusan Gupta <bgupta@micro.caltech.edu>) The CAzM program that was developed and offered by MCNC, has been licensed for distribution by Tanner Research, Inc. of Pasadena, CA and all future product availability and support is available from Tanner Research. The program as offered by Tanner Research is a commercial pro- duct and is now named T-Spice. This Spice-like simulator offers table- based model evaluations for fast simulation performance, as well as, included analytical models for use with digital and analog circuits. Improvements to the CAzM models have also been made. Tanner Research offers an optional Advance Model Library of charged controlled models that includes an accurate, physically-based MOSFET model that is continu- ous over all transistor regions of operations (including subthreshold), and scales to submicron channel lengths. User defined models of any cus- tom component or circuit written in "C" can be readily linked to T-Spice as a general n-terminal device. Pricing is $995 for the simulator and $1,245 with the Advance Model Library and Waveform Viewer. Universities are offered a 75% discount. A modeling and extraction service is also provided by Tanner Research to generate functional or transistor level circuit simulation models for user supplied devices. The extraction ser- vice provides extracted model parameters for existing circuit simulation models, such as SPICE models, Tanner's own charge controlled MOS models, or user's proprietary models. In addition, software is available to aid users in extracting model parameters in house. For more information con- tact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 42: Galaxy CAD, integrated environment for digital design for Macintosh Thanks to Simon Leung <sleung@sun1.atitech.ca> The Galaxy CAD System is an integrated environment for digital design and for rapid prototyping of CAD tools and other software. The system currently includes schematic capture and simulation of both low-level and high-level digital designs and is being expanded to include physical design tools. Galaxy runs on a number of 680X0 platforms, including the Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST. Others will be added according to demand. The Galaxy CAD System is an ideal environment for teaching digital design. It has been used successfully for both introductory logic design and computer design courses at Wisconsin. Some of the features of Galaxy that make it suitable for education are: 1. Integrated multiple-window environment: All Galaxy tools run concurrently in a multiple window environment. Copying data from one window to another is simple. Any number of simulation sessions can be active simultaneously. 2. Hierarchy: the schematic editor and simulator are both fully hierarchical. Building hierarchical designs is simple, including creating symbols for modules. The simulator is a true hierarchical simulator: it does not require a time-consuming macro-expansion step. 3. Integrated editing and simulation: Designs are edited and simulated in the same environment. Simulation input and output can be shown directly on schematics, allowing direct manipulation of net values. Unlike other products, Galaxy does not require modification of the schematic to insert "switch" and "light" components. In addition, Galaxy allows display of bus values in hexadecimal directly on schematics to simplify debugging of high-level designs. Simulation I/O can also use waveforms, text files, and tables. 4. Faults: Stuck-at faults can be introduced on the schematic editor and simulated immediately without rebuilding the simulation model. This provides an excellent way to display the effects of faults. 5. Buses: Galaxy supports specification and simulation of bus structures, including complex extractions, fanouts, and bit reversal. Buses are specified by annotating nets with text. For simulation, buses are kept intact so that multiple-bit high-level components can be used. Galaxy includes a library of register-transfer components suitable for high-level computer design and simulation. 6. Alternate specification of designs: In addition to schematics, Galaxy users can specify design modules using a textual HDL (GHDL) and using hardware flowcharts and state diagrams. A hierarchical design can mix these representations as desired. 7. High-quality PostScript output: Galaxy schematics are of excellent quality. Gates are drawn according to standard practices, e.g., OR gates are drawn with the correct circular arcs and not ellipses. 8. Uniform user interface: Galaxy tools have the same user interface on all platforms, reducing student learning curves. In fact, the same tool OBJECT CODE runs on all platforms due to the unique structure of Galaxy. 9. Adding new simulation primitives is straightforward. 10. No cost: Galaxy is available for free via anonymous FTP (Apple Macintosh version). Other versions will be made available based on demand. Galaxy is also an excellent environment for rapid prototyping of new CAD tools. By building on top of available resources, we have been able to prototype new tools in days or weeks that would ordinarily have taken months or years. For more information, send e-mail. To obtain Galaxy CAD, connect to "eceserv0.ece.wisc.edu:pub/galaxy" using FTP. Log in as "anonymous" with password "guest". Galaxy is in direc- tory "pub/galaxy". The file "README" in that directory gives further instructions. Please register as a user by sending e-mail to "beetem@engr.wisc.edu". John F. Beetem ECE Department University of Wisconsin - Madison Madison, WI 53706 USA (608) 262-6229 beetem@engr.wisc.edu 43: WireC graphical/procedural system for schematic information (From Larry McMurchie <larry@cs.washington.edu>) WireC is a graphical specification language that combines schematics with procedural constructs for describing complex microelectronic systems. WireC allows the designer to choose the appropriate representation, either graphical or procedural, at a fine-grain level depending on the characteristics of the circuit being designed. Drawing traditional schematic symbols and their interconnections provides fast intuitive interaction with a circuit design while procedural constructs give the power and flexibility to describe circuit structures algorithmically and allow single descriptions to represent whole families of devices. The procedural capability of WireC allows other CAD tools to be incor- porated into the design system. For example, we have defined an inter- face to the SIS logic synthesis system wherein the designer can represent part of the system behaviorally. WireC invokes logic synthesis on these components to produce a structural description that can be incorporated into the rest of the design. Libraries of devices defining a particular netlist output format may be defined by the user. The libraries currently distributed with WireC include a default CMOS gate library whose output is the SIM format. This format can be simulated with COSMOS or IRSIM and compared against a cir- cuit extracted from layout. This library also includes devices that allow a behavioral description to be synthesized and mapped using MIS or SIS and incorporated into a larger circuit. Another library is the xnf library for designing systems with Xilinx FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC, this library contains devices specific to the 2000 and 3000 series Xilinx LCA's. In addition to drawing the devices explicitly, one can represent parts of a circuit with equations and have these synthesized automati- cally. Currently in progress is a library of CMOS gates for Cascade Design Automation's ChipCrafter product. WireC provides a mixed schematic/procedural design frontend for ChipCrafter, which uses module generation, timing analysis and place and route software to create a phy- sical layout from the WireC design specification. WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed Tellman. We are interested in any libraries you may develop and will provide a limited degree of support. WireC requires an X-Windows compatible environment and a C++ compiler such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet. For details send mail to larry@cs.washington.edu ebeling@cs.washington.edu 44: LateX circuit symbols for schematic generation (From Adrian Johnstone <adrian@cs.rhbnc.ac.uk>) A set of circuit schematic symbols are available for use in LaTeX picture mode. The set includes all basic logic gates in four orientations, FETs, power supply pins, transmission gates, capacitors, resistors and wiring T-junctions. All pins are on a 1mm grid and the symbols are designed to be easily used with Georg Horn's TeXcad program: we even supply you with a palette picture file that displays all 52 symbols in a compact grid that you can cut and paste from within TeXcad. Each symbol lives in its own .mac file and is defined as a 'savebox' so as to reduce memory con- sumption. You must add the [bezier] option to your 'documentstyle' com- mand. A small manual is provided in both Postscript and .dvi forms. The files lcircuit.zip and lcircuit.tar are available for anonymous ftp from cscx.cs.rhbnc.ac.uk:pub/lcircuit (134.219.200.45). I will also be uploading them to various ftp servers in the coming week. 45: Tanner Research Tools (Ledit and LVS) (From Bhusan Gupta <bgupta@micro.caltech.edu>) Low cost, yet very powerful commercial ASIC design tools are available from Tanner Research, Inc. in Pasadena, CA. These products are used by industry and universities alike. Tanner's products are nominally priced at $995 per program, with a combined package named L-Edit Pro available for $3,495 on the PC. Universities are offered a 75% discount. Here is a list of their current programs: L-EditTM : A full-custom layout editor with CIF and GDSII input/output. Features a 32-bit coordinate space, all-angle geometry, unlimited hierarchy and number of layers. The L-Edit Pro package includes L-Edit/DRC for design rule checking, L-Edit/SPR for automatic standard cell placement and routing, L-Edit/Extract for extracting transistors, capacitors, resistors and generic devices for SPICE-level simulation or comparison to a schematic and LVS ,a netlist comparison tool for topological and parametrical verification. Optional layout libraries are also available. T-Spice: Circuit level simulator (See item 41 for detail GateSimTM : Gate-level simulator. A full array of technology mapping libraries are also available. Products are available for the PC, Macintosh, Sun and Hp UNIX platforms. For more information contact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 46: SIMIC, a full-featured logic verification simulator. (From comp.archives.msdos.announce) SIMIC is a full-featured logic verification simulator. It has been demonstrated that SIMIC can uncover a number of critical design errors that other simulators miss. SIMIC has shown superior accuracy and throughput when compared to competitive products. Here are some of SIMIC's important features: - Mixed-mode simulation allows the free intermixture of true bilateral switches (ideal and resistive), gate, plus functional level built-in and user defined primitives. - A wide variety of output, whose detail, content and format are, to large extent, user defined. - A large repetoire of simulation options and controls that can be applied interactively, or in batch operation, and simplify trouble-shooting of your design. - Automated Test equipment emulation, allows debugging test programs using SIMIC troubleshooting techniques. - Sophisticated hazard analysis including: Spike, Pulse, Conflict, Oscillation, Setup, Hold, Pulse-width, Near (what-if) detection, among others. Hazard propagation is also supported. The student version of SIMIC is limited to a maximum of 500 elements (parts). In all other respects it is the same program as the commercial offering. The PC student version requires a 386 or better and at least 2 Meg of memory. Both a DPMI and a VCPI version are included in the pack- age. Both versions require EMS *NOT* be disabled. SIMIC is also avail- able on Sun and other platforms. The latest version is 1.02.00. The changes from revision 1.00.04 are: Bug Fixes: - Rams properly handled by circuit compiler. - BTG (Ideal switches) compiled correctly with dynamic delays. - By-name pin connections accepted by circuit compiler. - JK Flip-flop timing checks can now be disabled. Enhancements: - Reduction in storage requirements for small RAMS. - Fault Sensitization analysis added. - Fault Simulation and grading added. This revision can be taken from oak.oakland.edu:pub/msdos/electrical , or wuarchive.wustl.edu:mirrors/msdos/electrical . The files in question are sim120bn.zip (Simic logic and fault simulator plus examples) and sim120dc.zip (Simic Engineering and User's Guides). 47: LASI CAD System, IC and device layout for IBM compatibles (from Mike Fitsimmons <mikef@hendrix.ece.uiuc.edu>) On behalf of the author I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1:<msdos.cad> LASI41A.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41B.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41C.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASIDEMO.ZIP LASI v4.1 DEMO drawing: unzip in The LASI CAD System has been developed to do integrated circuit and dev- ice layout on almost any IBM compatable personal computer. LASIDEMO is a small IC layout to be used as a demonstration when first learning to use LASI. I offered to pay the author for some sort of site license for this pro- gram, but he refused, saying that he actually wants educational institu- tions to use it for free. What a guy! 48: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles (from <pcc@minster.york.ac.uk>) I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1:<msdos.graphics> EEDRAW24.ZIP Electrical Engineering drawing (with layers) This is the 2.4 release of EEDRAW, an electrical/electronic diagramming tool for the IBM PC. pd1:<msdos.graphics> EEDSRC24.ZIP C sources for EEDRAW24.ZIP program. TC/BC++ This is the source of the EEdraw 2.4 program. Please read the readme file in the primary archive for information on other source programs needed such as the Libary files. 49: MagiCAD, GaAs Gate Array Design through MOSIS (from Tom Smith <tsmith@mayo.edu>) The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system is a package which provides a comprehensive design environment for the development of digital systems, from initial concept to post-layout verification of integrated circuits (ICs). MagiCAD focuses on the development of high-speed Gallium Arsenide (GaAs) gate array designs. Specialized electromagnetic simulation tools are provided to address high clock rate issues such as crosstalk and reflections, which become more important as clock rates exceed several hundred MHz or signal edge rates become less than 500 pico- seconds. MagiCAD provides all the necessary tools for high clock rate GaAs IC design, and is also integrated with non-Mayo circuit, logic, and fault simulators. MagiCAD provides a lower risk approach than full-custom design for universities wishing to perform digital GaAs design through MOSIS. This is done by providing a gate array design environment where low-level transistor design and layout issues have already been solved and abstracted into a technology library of pre-defined cells. This frees the student or researcher to solve the still challenging tasks of system and gate-level design and layout to get high clock rate chips fabricated through MOSIS that meet all specifications. MagiCAD supports hierarchical, top-down, middle-out, or bottom-up development styles. MagiCAD has been used in the design of many GaAs chips that have been successfully fabricated. The MagiCAD electromagnetic modeling tools have been used in the analysis of many actual packages, multi-chip modules (MCMs), and printed circuit boards (PCBs), uncovering and avoiding problems that are commonly associated with high-frequency, fast edge-rate designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a MagiCAD technology library, and has been used for both gra- duate and undergraduate student chip designs. Functionality that has been integrated into MagiCAD includes: o Vitesse VSC2K GaAs gate array technology library o Database which integrates all tools o Schematic entry through a general purpose graphics editor o Circuit simulator o Logic and timing simulators o Fault analysis o Place and route tools o Layout verification tools o Retargeting from generic design to specific technology o Output to standard GDSII format for mask creation o Electromagnetic analysis - Cross section entry with graphics editor - Multilayer multiconductor transmission line (MMTL) modeling - Network tool for solving cases with many transmission line components - Lossy and non-lossy cases - Frequency and time domain result displays - Used for analyzing complex design paths, through chip, MCM, and PCB The Vitesse VSC2K has the following characteristics: o HGaAs-2 (TM) process o 2700 available gates o Enhancement/depletion MESFET process o 80 signal pads o 2 GHz flip-flop toggle rates o 40 power, ground pads o 280 psec loaded gate delays o 2.4 watts maximum o 170 mils x 135 mils o ECL or TTL I/O o 132 pin LDCC package available o 2 routing layers The Mayo Foundation has used MagiCAD to design several VSC2K designs that have been fabricated through both MOSIS and Vitesse. These designs have measured operating frequencies of 500 MHz to 1 GHz, depending upon the section of the circuit being tested. The general application thrust of these designs has been components which are being used to evaluate MCM technologies for high speed systems, as well as high speed data generation and acquisition circuits. The University of Wisconsin - Milwaukee has used MagiCAD to design several VSC2K designs that have been fabricated through MOSIS. These designs have simulated clock rates from 100 MHz to 600 MHz. The general application thrust of these designs has been components of digital signal processors with medical image processing applications. The descriptions of these VSC2K personalizations that have been designed and fabricated include: o 8-bit Booth's algorithm multiplier o 4-bit arithmetic logic unit o 8-bit combinatorial multiplier o 24-bit carry look-ahead adder The Defense Advanced Research Projects Agency (DARPA) has authorized and funded Mayo to supply MagiCAD to universities in the U.S. for research and educational purposes. The direct cost to the universities for the MagiCAD software itself is zero (although there may be costs for any non-Mayo software that universities may want, as well as possible costs to get the proper hardware/software platform). Mayo-supplied MagiCAD training and support costs to these institutions is funded by DARPA, and is therefore free to the universities. While the MagiCAD tools are presently only available for VAX/VMS environ- ments, work is presently underway to port MagiCAD to POSIX-compliant platforms (POSIX is the IEEE "UNIX-like" portable operating system defin- ition). First POSIX platforms presently planned to port to include DECs- tations and HP workstations, likely availability of MagiCAD on these platforms is second half of 1993.