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Magazyn Enter 1999 January
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ctchip34
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UMC481A.CFG
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1993-01-25
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9KB
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281 lines
;UM82C481A
INDEXPORT=22H
DATENPORT=24H
INDEX=90H ;Integrated Memory Controller Identification Register
;*******************************************************
BIT=7654321 ; Version number, read only .
; First version is 01H. The 82C391A version is 02H.
INDEX=91H ;Wait State Configuration Register
;*******************************************************
BIT=7 ;Reserved
BIT=6 ;Cache Read Hit Burst Option (valid only if CPU is 80486)
0=fast cache read hit
1=normal cache read hit
BIT=5 ;Reserved
BIT=4 ;Cache Write Hit Option (valid only if CPU is 80486)
0=fast cache write hit
1=normal cache write hit
BIT=3 ;Reserved
BIT=2 ;DRAM Type
0=page mode DRAM
1=fast page mode DRAM
BIT=10 ;DRAM Wait State(s)
00=2 wait states
01=reserved
10=1 wait state
11=0 wait state
INDEX=92H ;Cache Control Register
;*******************************************************
BIT=7 ;0/1 Non-cacheable Block 2 Enable
BIT=6 ;Non-cacheable Block 1 Enable
0=disable (cacheable)
1=enable (non-cacheable)
BIT=5 ;0/1 Write Back Enable on Cache Read miss
BIT=4 ;Reserved
BIT=3 ;Cache RAM Size
0=two banks of cache RAM (8 pieces)
1=one bank of cache RAM (4 pieces)
BIT=21 ;Cache Line Size
00 16
01 reserved
10 8
11 4
BIT=0 ;0/1 Cache Enable
INDEX=93H ;Tag Address Comparison Register
;*******************************************************
BIT=7 ;Main Memory Above 16 MB Cacheability
0=non-cacheable
1=cacheable
BIT=6 ;Math Coprocessor Ready Delayed By 1 T-state
0=Delay the math coprocessor ready signal from being
presented to CPU by 1 T-state
1=Don't delay the math coprocessor ready signal
BIT=5 ;Check ELBA# pin in T1 or T2 state (valid only if
CPU is 80486)
0=check ELBA# signal in T1
1=check ELBA# signal in T2
BIT=43210 ;Cache RAM size
00000= 1MB
10000=512KB
11000=256KB
11100=128KB
11110= 64KB
11111= 32KB
INDEX=94H ;Non-cacheable Block 1 High Address Register
;*******************************************************
BIT=76 ;Reserved
BIT=543210 ;Non Cacheable Hiaddress Block 1: A25-A20
INDEX=95H ;Non-cacheable Block 1 Low Address Register
;*******************************************************
BIT=76543210 ;Non Cacheable Loaddress Block 1: A19-A12
INDEX=96H ;Non-cacheable Block 1 Size Register
;*******************************************************
BIT=76543210 ;Non-cacheable Size
11111111= 4KB
11111110= 8KB
11111100= 16KB
11111000= 32KB
11110000= 64KB
11100000=128KB
11000000=256KB
10000000=512KB
00000000= 1MB
INDEX=97H ;Non-cacheable Block 2 High Address Register
;*******************************************************
BIT=7 ;DMA CAS timing delay
0=no CAS delayed,
1=CAS delayed by 1 T
BIT=6 ;E segment (000Exxxx\H) location
0=E segment on system board
1=E segment on AT bus
BIT=54 ;Reserved
BIT=3 ;SWTRBO# (80386 only)
0=normal
1=software de-TURBO by forcing cache read miss
BIT=2 ;FALTH (80386 only)
0=normal
1=Force write back regardless the Dirty Tag
BIT=10 ;Non-cacheable Low Address Block 2 A25-A24
INDEX=98H ;Non-cacheable Block 2 Low Address Register
;*******************************************************
BIT=76543210 ;Non-cacheable Low Address A23-A16
INDEX=99H ;Non-cacheable Block 2 Size Register
;*******************************************************
BIT=76543210 ;Non-cacheable Block 2 Size
11111111= 64KB
11111110=128KB
11111100=256KB
11111000=512KB
11110000= 1MB
11100000= 2MB
11000000= 4MB
10000000= 8MB
00000000= 16MB
INDEX=9AH ;DRAM Configuration Register
;*******************************************************
BIT=76 ;Bank 4
00=no DRAM installed
01=256Kx1 (256Kx4) DRAM installed
10=1Mx1 (1Mx4) DRAM installed
11=4Mx1 (4Mx4) DRAM installed
BIT=54 ;Bank 3
00=no DRAM installed
01=256Kx1 (256Kx4) DRAM installed
10=1Mx1 (1Mx4) DRAM installed
11=4Mx1 (4Mx4) DRAM installed
BIT=32 ;Bank 2
00=no DRAM installed
01=256Kx1 (256Kx4) DRAM installed
10=1Mx1 (1Mx4) DRAM installed
11=4Mx1 (4Mx4) DRAM installed
BIT=10 ;Bank 1
00=no DRAM installed
01=256Kx1 (256Kx4) DRAM installed
10=1Mx1 (1Mx4) DRAM installed
11=4Mx1 (4Mx4) DRAM installed
INDEX=9BH ;E,F Segment Control Register
;*******************************************************
BIT=76 ;Hidden Memory Remapping to top of Memory
00=no memory remapping
01=256K (A, B, D, E segments) remapped
10=384K (A-F segments) remapped
11=reserved
BIT=5 ;E Segment Cacheability
0=non-cacheable
1=cacheable
BIT=4 ;Shadow RAM for E Segment
0=ROM
1=Shadow RAM
BIT=3 ;Write Protect E Segment
0=no write protected
1=write protected
BIT=2 ;F Segment Cacheability
0=non-cacheable
1=cacheable
BIT=1 ;Shadow RAM for F Segment
0=ROM
1=Shadow RAM
BIT=0 ;Write Protect F Segment
0=no write protected
1=write protected
INDEX=9CH ;C, D Segment Cacheability Register
;*******************************************************
BIT=7 ;0/1 000DC000H-000DFFFFH Region Cacheability
BIT=6 ;0/1 000D8000H-000DBFFFH Region Cacheability
BIT=5 ;0/1 000D4000H-000D7FFFH Region Cacheability
BIT=4 ;0/1 000D0000H-000D3FFFH Region Cacheability
BIT=3 ;0/1 000CC000H-000CFFFFH Region Cacheability
BIT=2 ;0/1 000C8000H-000CBFFFH Region Cacheability
BIT=1 ;0/1 000C4000H-000C7FFFH Region Cacheability
BIT=0 ;0/1 000C0000H-000C3FFFH Region Cacheability
INDEX=9DH ;C, D Segment Shadow RAM Register
;*******************************************************
BIT=7 ;Shadow RAM for 000DC000H-000DFFFFH Region
0=ROM
1=Shadow RAM
BIT=6 ;Shadow RAM for 000D8000H-000DBFFFH Region
0=ROM
1=Shadow RAM
BIT=5 ;Shadow RAM for 000D4000H-000D7FFFH Region
0=ROM
1=Shadow RAM
BIT=4 ;Shadow RAM for 000D0000H-000D3FFFH Region
0=ROM
1=Shadow RAM
BIT=3 ;Shadow RAM for 000CC000H-000CFFFFH Region
0=ROM
1=Shadow RAM
BIT=2 ;Shadow RAM for 000C8000H-000CBFFFH Region
0=ROM
1=Shadow RAM
BIT=1 ;Shadow RAM for 000C4000H-000C7FFFH Region
0=ROM
1=Shadow RAM
BIT=0 ;Shadow RAM for 000C0000H-000C3FFFH Region
0=ROM
1=Shadow RAM
INDEX=9EH ;C, D Segment Write Protect Register
;*******************************************************
BIT=7 ;0/1 Write Protect 000DC000H-000DFFFFH Region
BIT=6 ;0/1 Write protect 000D8000H-000DBFFFH Region
BIT=5 ;0/1 Write protect 000D4000H-000D7FFFH Region
BIT=4 ;0/1 Write protect 000D0000H-000D3FFFH Region
BIT=3 ;0/1 Write protect 000CC000H-000CFFFFH Region
BIT=2 ;0/1 Write protect 000C8000H-000CBFFFH Region
BIT=1 ;0/1 Write protect 000C4000H-000C7FFFH Region
BIT=0 ;0/1 Write Protect 000C0000H-000C3FFFH Region
INDEX=9FH ;DRAM Configuration Detect Register
;*******************************************************
BIT=76 ;Reserved
BIT=5 ;Force DRAM row address MA10 high
0=row address MA10=A23
1=row address MA10=VCC
BIT=4 ;Force DRAM row address MA9 high
0=row address MA9=A23
1=row address MA9=VCC
BIT=3 ;1/0 Map address space of bank 4 to bank 1
BIT=2 ;1/0 Map address space of bank 3 to bank 1
BIT=1 ;1/0 Map address space of bank 2 to bank 1
BIT=0 ;1/0 Map address space of bank 1 to bank 1